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Managing Two SPI Masters and One SPI Flash Slave - KBA225990


Managing Two SPI Masters and One SPI Flash Slave - KBA225990

Author: MaxW_71           Version: **

Translation - Japanese: 2つのSPIマスターと1つのSPIフラッシュ スレーブの管理 - KBA225990 - Community Translated (JA)


Can I connect two MCUs, one single-IO and one quad-IO, to a single S25FL128S, where the single-IO MCU holds the quadIO MCU in RESET until it is done?


Yes, there are many applications that use this arrangement. One common setup has a single-IO MCU connected to the flash for field updates over CAN, and a quad-IO MCU using the high-speed IO to load an application from flash. The single-IO MCU holds the quad-IO MCU in reset until it finishes with the flash, at which time the quad-IO MCU is released from RESET to take ownership of the flash. For these applications, the single-IO MCU does not retake the master role until the next system restart; see below for special considerations.

One critical point is the flash is a single-user device, so some means must be provided for ensuring only one master accesses the flash at a time.

  • Having the “primary master” unilaterally put the “secondary master” in reset at system startup is fine if the primary master never takes back control of the flash until after system sleep or shutdown (this is the case described in the opening paragraph).
  • If the primary and secondary masters need to share the flash after system startup, it is best practice for one master to wait to take control of the flash until the other master releases it, via some mutual-exclusion mechanism.
  • A combination of both methods could also be used, wherein the

Another critical point is that the flash must be configured to work with both quad-IO and single-IO. Cypress recommends setting the QUAD bit to 1 in the configuration register and using this as your “standard state” for configuring the flash. This setting enables the quad-IO master to use quad-IO, and it also enables the single-IO master to use single-IO.

Setting QUAD=1 works well if the single-IO (or dual-IO) master is using only SI/IO0 and SO/IO1 – that is it is not using the WP# or HOLD# functions on the multiplexed WP#/IO2 and HOLD#/IO3 pins. If your single/dual-IO processor is using either WP# or HOLD#, then the QUAD bit will need to be changed to the correct setting before each master uses the flash.

Using QUAD=1 is as the standard state for both masters is the best way. This is because a power failure or RESET during a WRR command can corrupt the flash registers. Setting QUAD=1 once in production and never changing it thereafter is the best way to avoid this problem.

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‎Dec 25, 2018 10:34 PM
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