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MOTIX™ 6EDL7141: Register mapping in BPA Motor Control GUI - KBA236258

MOTIX™ 6EDL7141: Register mapping in BPA Motor Control GUI - KBA236258

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Version: **

Context:

The MOTIX™ 6EDL7141 registers’ values can be changed via battery-powered application (BPA) motor control GUI or DAVE project (6EDL7141_SPILIB_XMC1400). The final released firmware will be based on ModusToolbox™, but for this SPILIB demonstration, it’s based on DAVE IDE. BPA motor control GUI is a graphical interface for evaluation boards 6EDL7141 (EVAL_6EDL7141_TRAP_1SH) and IMD700A (EVAL_IMD700A_FOC_3SH). This GUI provides easy access to play around with the MOTIX™ 6EDL7141 registers for users. A brief relation between the MOTIX™ 6EDL7141 registers and the BPA motor control GUI is shown in the below table.

Workaround:

The 6EDL7141 smart gate driver software features are divided into four categories:

  1. Power supply
  2. PWM and three-phase gate driver
  3. Current sense amplifier and over-current protection (OCP)
  4. Housekeeping

 

1   Power supply

If PVCC set point is set to 15 V, Charge Pump Pre-charge is enabled, Buck Converter frequency is 500 kHz, DVDD soft start time is 500 us, DVDD TurnOn Delay is 600 us and DVDD OCP threshold is 300 mA then Supply configuration register (SUPPLY_CFG) is 1 10 0 xx 0100 01 xx 01. If Charge Pump Clock Frequency is 390.625 kHz and Charge Pump Spread Spectrum is enabled then Charge Pump Configuration is (CP_CFG) is 0000000000000 0 01.

Software Feature

BPA GUI Setting

6EDL7141 Register Bitfield

Condition

6EDL7141 Register Setting

 

 

 

 

 

 

 

 

Power Supply

1.png

SUPPLY_CFG

x xx x xx xxxx xx xx 01

PVCC (15V) (01) (PVCC_SETPT)

 

 

 

SUPPLY_CFG

1 10 0 xx 0100 01 xx 01

CP_CFG

0000000000000 0 01

2.png

CP_CFG

0000000000000 x 01

Charge Pump Clk Frq (CP_CLK_CFG) (390.625 kHz)

3.png

CP_CFG

0000000000000 0 xx

Charge Pump Spread Spectrum (CP_CLK_SS_DIS) (En)

4.png

SUPPLY_CFG

1 xx x xx xxxx xx xx xx

Charge Pump Pre-charge (CP_PRECHARGE_EN) (En)

5.png

SUPPLY_CFG

x xx 0 xx xxxx xx xx xx

Buck converter frq (BK_FREQ) (500kHz)

6.png

SUPPLY_CFG

x xx x xx 0100 xx xx xx

DVDD Soft Start Time (DVDD_SFTSTRT) (500us)

7.png

SUPPLY_CFG

x 10 x xx xxxx xx xx xx

DVDD Turn On Delay (DVDD_TON_DELAY) (600us)

8.png

SUPPLY_CFG

x xx x xx xxxx 01 xx xx

DVDD OCP Thd (DVDD_OCP_CFG) (300mA)

 

PWM and three-phase gate driver


If PWM Mode is 1 PWM with Hall sensors mode, PWM Freewheeling Mode is Active FW, Brake configuration is High side brake and PWM alternate recirculation is enabled, then PWM configuration register (PWM_CFG) is
000000000 1 01 0 011. If Dead time rising is 520 ns and Dead time falling is 520 ns, then Dead time configuration register (DT_CFG) is 00000101 00000101. If High side source current is 200mA and High side sink current is 200mA, Low side source current is 200mA and Low side sink current is 200mA, then Current Drive Configuration (IDRIVE_CFG) is 1011 1011 1011 1011. If Pre-charge source current is 200mA and Pre-charge sink current is 200mA, and Pre-charge is enabled, then Current Drive Pre-Configuration (IDRIVE_PRE_CFG) is 0000000 0 1011 1011. If Source and sink current time periods TDrive1, TDrive2, TDrive3, and TDrive4 are 100 ns, then Timing Drive Source Configuration (TDRIVE_SRC_CFG) is 00001010 00000110 and Timing Drive Sink Configuration (TDRIVE_SINK_CFG) is 00001010 00000110.

Software Feature

BPA GUI Setting

6EDL7141 Register Bitfield

Condition

6EDL7141 Register Setting

 

 

 

 

 

PWM & 3 Phase Gate Driver

1.png

PWM_CFG

000000000 x xx x 011

PWM_Mode (1PWM with Hall sensors) (011)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWM_CFG

000000000 1 01 0 011

DT_CFG

00000101 00000101

IDRIVE_CFG

1011 1011 1011 1011

IDRIVE_PRE_CFG

0000000 0 1011 1011

TDRIVE_SRC_CFG

00001010 00000110

TDRIVE_SINK_CFG

00001010 00000110

2.png

PWM_CFG

000000000 x xx 0 xxx

PWM Freewheeling Mode (Active freewheeling)(PWM_FREEW_CFG) (0)

3.png

PWM_CFG

000000000 x 01 x xxx

Brake Configuration (BRAKE_CFG) (01)

4.png

PWM_CFG

000000000 1 xx x xxx

Alternate Recirculation (PWM_RECIRC) (1En)

5.png

DT_CFG

xxxxxxxx 00000101

DT_CFG

00000101 xxxxxxxx

Dead time rising (DT_RISE) (520ns)

Dead time falling (DT_FALL) (520ns)

6.png

IDRIVE_CFG

xxxx xxxx xxxx 1011

IDRIVE_CFG

xxxx xxxx 1011 xxxx

High side source current

(IHS_SRC) (200mA)

High side sink current

(IHS_SINK) (200mA)

7.png

IDRIVE_CFG

xxxx 1011 xxxx xxxx

IDRIVE_CFG

1011 xxxx xxxx xxxx

Low side source current

(ILS_SRC) (200mA)

Low side sink current

(ILS_SINK) (200mA)

8.png

IDRIVE_PRE_CFG

0000000 x xxxx 1011

IDRIVE_PRE_CFG

0000000 x 1011 xxxx

Pre-charge source current (I_PRE_SRC) (200mA)

Pre-charge sink current (I_PRE_SINK) (200mA)

9.png

IDRIVE_PRE_CFG

0000000 0 xxxx xxxx

Pre-charge (I_PRE_EN) (0)(En)

10.png

TDRIVE_SRC_CFG

xxxxxxxx 00000110

TDRIVE_SRC_CFG

00001010 xxxxxxxx

TDRIVE_SINK_CFG

xxxxxxxx 00000110

TDRIVE_SINK_CFG

00001010 xxxxxxxx

TDRIVE1 (100ns)

 

TDRIVE2 (100ns)

 

TDRIVE3 (100ns)

 

TDRIVE4(100ns)

 

Current sense amplifier and over-current protection (OCP)


If Current Sense Amplifier B is enabled, Current sense gain of 8x via register pin, Blanking time of 100 ns, DC calibration is disabled, OCP deglitch time of 4 us, and OCP fault trigger is 16 OCP events, then Current Sense Amplifier Configuration (CSAMP_CFG) is
01 10 0 0010 010 0 001. If Current Sensing Mode is Shunt Resistor sensing, External Offset is disabled, Amplifier Auto Zero configuration is internally triggered, OCP positive threshold is 200 mV, OCP negative threshold is 200 mV, PWM Truncation is enabled, OCP fault latching is enabled, Brake on OCP is disabled, and Negative OCP is enabled, then Current Sense Amplifier Configuration 2 (CSAMP_CFG2) is 00 0 0 00 0 0 1 0011 0011. If Amplifier Timing Mode is Low Switches High, then Sensor Configuration (SENSOR_CFG) is 000000000 00 x xxxx. If Internal Offset of 5/12 DVDD is selected, then Supply Configuration register (SUPPLY_CFG) is x xx x xx xxxx xx 01 xx.

Software Feature

BPA GUI Setting

6EDL7141 Register Bitfield

Condition

6EDL7141 Register Setting

 

 

 

 

 

 

 

 

 

Current Sense Amplifier & Over Current Protection

1.png

CSAMP_CFG

xx xx x xxxx 010 x xxx

Current sensing by the single shunt (phase B enabled) (010) (CS_EN)

 

 

 

 

 

 

 

 

 

 

 

 

CSAMP_CFG

01 10 0 0010 010 0 001

CSAMP_CFG2

00 0 0 00 0 0 1 0011 0011

SENSOR_CFG

000000000 00 x xxxx

SUPPLY_CFG

x xx x xx xxxx xx 01 xx

2.png

CSAMP_CFG

xx xx x xxxx xxx 0 001

Gain 8x(001)(CS_GAIN) via register configuration(0)(CS_GAIN_ANA)

3.png

CSAMP_CFG2

xx x x xx x 0 x xxxx xxxx

Shunt resistor sensing (0)(CS_MODE)

4.png

SUPPLY_CFG

x xx x xx xxxx xx 01 xx

Internal Offset 5/12 DVDD(CS_REF_CFG)

5.png

CSAMP_CFG2

xx x 0 xx x x x xxxx xxxx

Use External Offset (Disable)

6.png

SENSOR_CFG

000000000 00 x xxxx

Amplifier Timing Mode(CS_TMODE)

7.png

CSAMP_CFG

xx xx x 0010 xxx x xxx

Blanking time (CS_BLANK) of 100ns (0010)

DC calibration is not enabled from BPA GUI

CSAMP_CFG

xx xx 0 xxxx xxx x xxx

No DC calibration (CS_EN_DCCAL)(0)

8.png

CSAMP_CFG2

00 x x xx x x x xxxx xxxx

Amplifier Auto zero config.(CS_AZ_CFG)(Int.)

9.png

CSAMP_CFG2

xx x x xx x x x 0011 0011

OCP Positive Thd(200mV)(CS_OCP_PTHR), OCP Negative Thd(-200mV)(CS_OCP_NTHR)

10.png

CSAMP_CFG2

xx x x 00 x x x xxxx xxxx

PWM Truncation(CS_TRUNC_DIS)

11.png

CSAMP_CFG

xx 10 x xxxx xxx x xxx

OCP deglitch time(CS_OCP_DEGLITCH) 4us (10)

12.png

CSAMP_CFG

01 xx x xxxx xxx x xxx

OCP fault trigger(CS_OCPFLT_CFG) 16 OCP events (01)

13.png

CSAMP_CFG2

xx x x xx x x 1 xxxx xxxx

OCP fault latching(CS_OCP_LATCH)

14.png

CSAMP_CFG2

xx x x xx 0 x x xxxx xxxx

Brake on OCP(CS_OCP_BRAKE)

15.png

CSAMP_CFG2

xx 0 x xx x x x xxxx xxxx

Negative OCP(CS_NEG_OCP_DIS)

 

Housekeeping


If Hall Sensor Deglitch time is 640 ns, Over-temperature Shutdown is enabled, then Sensor configuration register (SENSOR_CFG) is
000000000 xx 0 0001. If ADC measurement filter is 32 samples averaging filter and ADC PVDD measurement filter is 32 samples averaging filter, then ADC configuration register (ADC_CFG) is 00000000 00 10 x xx x. If Watch Dog timer is enabled, Watch Dog (WD) Input selection is VCCLS and VCCHS, WD Fault report is status+nFault, and WD period time is 100ms, then Watch Dog Configuration register (WD_CFG) is 0 1111101001 1 011 1. If Buck Converter WD is enabled, Rotor Lock detection time is 5s, Rotor Lock detection is enabled, WD fault latching is enabled, Brake on WD timer overflow is enabled, WD DVDD restart delay is 6 ms, WD DVDD Re-start Attempts is 2 attempts, then WD Configuration register 2 (WD_CFG2) is 000 0 100 1 1011 10 1 1.

Software Feature

BPA GUI Setting

6EDL7141 Register Bitfield

Condition

6EDL7141 Register Setting

 

 

 

 

 

 

 

 

 

 

 

 

 

Housekeeping

1.png

SENSOR_CFG

000000000 xx x 0001

Hall Sensor Deglitch Time (640 ns)(HALL_DEGLITCH)

 

 

 

 

 

 

 

 

SENSOR_CFG

000000000 xx 0 0001

ADC_CFG

00000000 00 10 x xx x

WD_CFG

0 1111101001 1 011 1

WD_CFG2

000 0 100 1 1011 10 1 1

OTP_PROG

00000000000 1110 x

2.png

SENSOR_CFG

000000000 xx 0 xxxx

Over-temperature Shutdown (0 En)(OTS_DIS)

3.png

ADC_CFG

00000000 xx 10 x xx x

ADC_CFG

00000000 00 xx x xx x

ADC Measurement filter (ADC_FILT_CFG) (32 samples averaging filter)

ADC PVDD Measurement Filter(ADC_FILT_CFG_PVDD) (32 samples)

4.png

WD_CFG

0 xxxxxxxxxx x xxx 1

 

WD_CFG

0 xxxxxxxxxx x 011 x

 

WD_CFG

0 xxxxxxxxxx 1 xxx x

 

WD_CFG

0 1111101001 x xxx x

Watch Dog Timer (WD_EN)(1 En)

WD Input Selection (WD_INSEL) (VCCLS and VCCHS)

WD Fault Report (WD_FLTCFG)(status register and pull down of nFAULT pin)

WD Period Time (WD_TIMER_T) (100ms 1001)

5.png

WD_CFG2

000 0 xxx x xxxx xx x x

WD_CFG2

000 x 100 x xxxx xx x x

WD_CFG2

000 x xxx 1 xxxx xx x x

Buck converter watchdog (WD_BK_DIS)(0 En)

Rotor lock detection time (WD_RLOCK_T)(5s)

Rotor lock detection (WD_RLOCK_EN)(1En)

6.png

WD_CFG2

000 x xxx x xxxx xx 1 x

WD_CFG2

000 x xxx x xxxx xx x 1

WD_CFG2

000 x xxx x 1011 xx x x

WD_CFG2

000 x xxx x xxxx 10 x x

WD Fault Latching (WD_EN_LATCH) (1 Flt Latched)

Brake on WD timer overflow (WD_BRAKE)(1)

WD DVDD restart delay (WD_DVDD_RSTSRT_DLY)(6 ms)

WD DVDD Re-start Attempts (WD_DVDD_RSTSRT_ATT)(2 attempts)

7.png

OTP_PROG

00000000000 1110 x

User ID (USER_ID) (14)

 

For more information on Registers of 6EDL7141 and BPA GUI, see 6EDL7141 DataSheet. Underlined ones are the bit changes in the register for that particular condition.

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