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Infineon® parallel NOR flash reference schematic - KBA234551

Infineon® parallel NOR flash reference schematic - KBA234551

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Community Translation: インフィニオン®パラレルNOR flash参考回路図 – KBA234551

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Infineon® parallel NOR flash devices can be connected directly with memory controllers without any additional components. A reference schematic diagram for Infineon® parallel NOR flash devices is given below using S29GL01GT.

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Figure: 1 Reference schematic diagram

Note: This schematic is true for a byte address processor connected to an x8/x16 flash configured in x16 WORD (DQ15) mode only. In x8 byte mode, DQ15 becomes A1 as the least significant bit of the address bus. In x16 word mode, A1 becomes DQ15 as the most significant bit of the data bus. The BYTE# pin is connected to VSS in x8 byte mode.

Best practices

  1. Perform signal integrity simulations using IBIS models available on the Infineon website before finalizing the design.
  2. Based on the signal integrity simulations, add series termination resistors to the DQ pins.
  3. Leave NC, DNU and RFU pins unconnected.
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