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In Aldec-HDL is there any way to name remerged signals other than VBUS#

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In Aldec-HDL is there any way to name remerged signals other than VBUS#

Question: In Aldec-HDL is there any way to name remerged signals other than VBUS#?

 

Answer:

Unfortunately, the "VBUS" designation is default. There is no way to rename these signals.

However, signal buses naturally contain the group signal name as the merged signal name. For instance, a signal bus defined in HDL code as std_logic_vector will automatically be collapsable to view all signals as a bus (hex or decimal output).

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‎Jan 01, 2012 03:24 PM
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