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How to set HSLI Interframe delay?

How to set HSLI Interframe delay?

Infineon_Team
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According the Datasheet, the HSLI aborts processing the communication when no dominant ("0") bus communication occurred longer than the interframe delay tframedly. The master needs to wait longer than tframedly between two consecutive frames. The interframe delay is configurable via the OTP.
It is recommended to set an interframe delay longer than the maximum expected recessive time (1) and shorter than the expected HSLI update period (2)

The two timings are explained here below:
(1) Interframe delay tframedly longer than the maximum expected recessive time
The transmission time of 8 bits + 1 bit stop + max time between bytes (depends on specific microcontroller's UART implementation)

  • tframedly > [bitTime] * [maximum recessive bit count + 1 bit stop + max time between UART bytes]
then,
  • tframedly > (1/HSLISPEED [bps]) * (8 bits + 1 bit stop + max time between UART bytes)

Max time between UART bytes is depending on the microcontroller, often is just 0.


(2) Interframe delay tframedly shorter than the expected HSLI update period in the application (example: application wants to send a DC_UPDATE every 10ms) minus the longest frame time I need to send within this period (which could be for instance DC_UPDATE for 14 bit duty cycle DLC6)

  • tframedly < (HSLIupdate_period - DC_UPDATE 14 bit count *(1/HSLIspeed[bps] )
if more commands have to be sent in the application HSLI update period, then the interframe delay has to be reduced further.
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