Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

How to implement Infineon NOR flash Verilog/VHDL model simulation? - KBA234316

How to implement Infineon NOR flash Verilog/VHDL model simulation? - KBA234316

Community Manager
Community Manager
Community Manager
100 sign-ins 50 questions asked 50 sign-ins

How to implement Infineon NOR flash Verilog/VHDL model simulation? - KBA234316

Version: **

The Verilog/VHDL model for Infineon NOR flash device is available to download here. After downloading the file, see Model Manual in the folder for implementation of the model. The following steps are to be performed:

  1. Check for the required files available in the folder
    • VHDL model: The model file model.vhd is located in the model directory. It relies on a set of functions defined in the files gen_utils.vhd and conversions.vhd. These 3 files comprise the minimum set of files for a behavioral VHDL simulation.
    • Verilog model: The model file model.v is located in the model directory. It does not depend on other files and can be run as-is in a behavioral Verilog simulation.
  2. Pre-load flash model in Behavioral simulations
    • Each instance of the model can be pre-loaded to simplify the simulation
    • Simulation starts up as if the flash memory had been programmed before and enters the simulation in a certain mode and contains certain data.
    • The pre-loading feature is controlled by 2 attributes
      • UserPreload
      • preload_file_name(s)
    • These attributes should be assigned to each instantiation of the model in the top-level netlist.
  3. Writing pre-load files
    • The test bench process loads default values into the memory array, CFI field, and protection bits.
    • The values can be overwritten by defining pre-load files for model instantiation in the test bench
      • mem_file_name: Loads memory array with data
      • prot_file_name: Lists protected sectors
      • Secsi_file_name: Loads Secure Silicon Sector (if available)
  4. Compiling model files:
    • VHDL: Following files needs to be compiled to the appropriate library
      • conversions.vhd: Compile to library FMF
      • gen_utils.vhd: Compile to library FMF
      • model.vhd: Compile to library work
    • Verilog: model.v can be compiled as it is.
  5. Simulating model files
    • For a basic simulation no files beyond the files used for compilation are required.
    • For performing timing simulation, the timing information needs to be provided as an SDF file.
    • Some models require the use of an SDF file for correct simulations. Follow the instructions provided by your simulator vendor to annotate the SDF files for simulation.
  6. Generating SDF files

    There are two methods for generating SDF files.

    • Method 1: Select the section with the desired speed grade (i.e. the OPN) in the FTM file. Copy and paste this section into the final SDF file for the overall simulation.
    • Method 2: For VHDL-only simulations, a global SDF file can be generated automatically if FTM files exist for each component of the overall simulation environment. The global SDF file can be created by executing the Perl script provided in the utilities directory. The Perl script is executed by entering:

perl mk_sdf_204.pl top_level.vhd // Unix environment

In case of any difficulties to perform simulation, please verify the following points:

  1. Make sure you are using the latest model downloaded from our website. Infineon NOR flash Verilog models are available here.
  2. The SDF file is used for the simulations