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Community Translation: AURIX™ TriCore™ CPUのCPU負荷を減らす方法は？ – KBA234357
Question: How to decrease the CPU load of an AURIX™ TriCore™ CPU?
Answer:
The following methods can be applied to offload CPU:
- Identification of functions and tasks which consume most of the loads:
Tools can be used to measure the durations of each task and the repartition of tasks over time: You can find on the Infineon website the list of our partners who can propose this kind of trace and real time monitoring tools.
In addition, some performance counters are available in each core. They can be used to measure the performance of CPU: CCNT (CPU Clock Count Register), ICNT (Instruction Count Register), and MxCNT (Multi Count Register x, x=1,2,3).
- Activation of cache and use of cacheable addresses in the software:
In each CPU, there are two types of cache: data cache and instruction cache. They can be individually activated to reduce the average access times to flash resources.
- Map critical resources in local RAM of the CPUy (y = 0,1,2).
CPUx will need 0 wait-state to access its local RAM.
Map the variables in DSPR (Data Scratch Pad RAM) of the CPU that accesses the most of the time.
Map code of critical functions in local PSPR (Program Scratch Pad RAM) of the CPUx which call this function.
- Use of compiler options:
Some options are available for each compiler to increase the execution speed of function and code sizes.
- Efficient addressing:
Faster execution time can be achieved using specific addressing types: customer will need less instructions to access resources (register, memory,…).
- Short addressing (Base + Long Offset addressing using global Base Registers (A0, A1, A8, A9) provides efficient data access in the address range of 64 KB).
- Near addressing (customer can use near segments to locate variables and constants (located in the first 16 KB of each TriCore™ 256 MB memory segment).
- Check the configuration of wait-states to access flash (Calculation formulas available in the user manual).
- Check clock is correctly configured (e.g., CPU, SRI (Shared Resource Interconnect), SPB (System Peripheral bus), …)
- Additional optimizations potential :
Instead of an emulation library, customers can use a single-precision Floating Point Unit (compiler option).
By setting a --no-double option the compiler treats variables of the type double as a float.
- Intrinsic functions:
Some intrinsic functions are proposed to use specific assembly instructions that have no equivalence in C.
- Critical functions/tasks can be optimized directing in assembler:
In this case, optimize the use of the TriCore™ superscalar pipeline (optimize delay time with the sequencing of instructions IP, LS, and LP).
The inline assembler can be directly used in C code (you can pass C variables as operands).
See the application note AP32168 for details.
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series
