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How is voltage sensed when sensing R is placed at LS or HS of TLD6098?

How is voltage sensed when sensing R is placed at LS or HS of TLD6098?

Infineon_Team
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The device has two distinct circuits to sense the voltage when the sensing resistor is placed at low side or at high side.

This is visible in the EC-Table 5 of the Datasheet. At different output voltages there are different bias currents for FBH and FBL pins (they are measured considering the sensing resistor at high side and at low side topology).

The device enters in high side sensing when the sensing voltage on FBH pin is higher than 2.8 V (VFBH1,1_HSS PRQ-265).

The device enters in low side sensing when the sensing voltage on FBH pin is lower than 2.1 V (VFBH1,1_LSS PRQ-266).

When the device is in low side sensing both the currents IFBL and IFBH flow out of the pins and this could cause an output voltage of 2V when using this device in SEPIC topology without output current (SET = 0 V or/and PWMI low).

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