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How does ERR bit set in SPIDER+ in parallel usage?

How does ERR bit set in SPIDER+ in parallel usage?

Infineon_Team
Employee
Employee
50 replies posted 25 likes received 25 replies posted

 

In case of parallel usage of OUT0 and OUT2

If both channel were latched by overload, both ERR0 and ERR2 are set.

If customer would clear the ERR bit by HWCR_OCL.OUTn command, they have to reset both ERR0 and ERR2.

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