Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob

Halting a peripheral when the CPU is halted - KBA235629

Halting a peripheral when the CPU is halted - KBA235629

IFX_Publisher2
Community Manager
Community Manager
Community Manager
1000 replies posted First like given 750 replies posted

Version:  **

When debugging an application, you may want to halt/pause/freeze peripherals when a debug event halts the CPU so that the peripheral state and the CPU execution state remain in sync. For example, the Cortex®-M SysTick timer automatically halts when the CPU is halted; however, the other peripherals in TRAVEO™ T2G require additional configuration steps. Peripherals that support such debug features have a corresponding trigger input connected to the TRAVEO™ T2G Trigger Multiplexer; an example is TCPWM_DEBUG_FREEZE_TR_IN.

In addition, the CPU halted information needs to enter the Trigger Multiplexer as a trigger output signal, e.g., CTI_TR_OUT[0]. It can be achieved by configuring the Arm® CoreSight® Cross-Trigger Interface (CTI) as described in KBA235072, that serves as a prerequisite for this KBA.

Based on the TRAVEO™ T2G CYT2B7 series, the following configuration example targets a TCPWM timer. The Trigger Multiplexer structure may differ slightly for other series MCUs; however, the general concept described here is applicable for all series.

1.1  CTI configuration

See KBA235072 for the required configuration. It is assumed that the “CPU halted” signal is routed to the CPUSS:CTI_TR_OUT[0] trigger output.

1.2   Trigger Multiplexer configuration

The “Trigger Multiplexer” section in the datasheet of the device shows that multiplexer groups 8 and 9 need to be configured in order to connect any CPUSS output trigger with the TCPWM_DEBUG_FREEZE_TR_IN trigger input.

BinduPriya_G_0-1654850678244.png


 Figure 1  Trigger Multiplexer

Using the definitions from the device header files and the Trigger Multiplexer driver APIs from the TRAVEO™ T2G Sample Driver Library (SDL), the mentioned connection can be established as follows:

// Route CTI_TR_OUT[0] trigger to TCPWM_DEBUG_FREEZE_TR_IN
Cy_TrigMux_Connect(TRIG_IN_MUX_9_CTI_TR_OUT0,       TRIG_OUT_MUX_9_TR_GROUP8_INPUT1, 0, TRIGGER_TYPE_LEVEL, 0);
Cy_TrigMux_Connect(TRIG_IN_MUX_8_TR_GROUP9_OUTPUT0, TRIG_OUT_MUX_8_TCPWM_DEBUG_FREEZE_TR_IN, 0, TRIGGER_TYPE_LEVEL, 0);

1.3  TCPWM configuration

After configuring the trigger route, the required TCPWM instance can be initialized using the SDL TCPWM driver APIs.

The main configuration structure used by the driver’s init function contains a boolean member called “debug_pause” which must be set to “true” if the respective TCPWM instance must halt when the CPU is halted.

cy_stc_tcpwm_counter_config_t const myCounterConfig =
{
    [...]
    .debug_pause = true,
    [...]
};
Cy_Tcpwm_Counter_Init(TCPWM0_GRP0_CNT0, &myCounterConfig);
[...]

The driver will then apply the value to the DBG_FREEZE_EN bit in the CTRL register of the respective TCPWM instance.

1.4   Test

To verify the configuration, observe the value of the COUNTER register of the TCPWM instance. Its value should not change while the CPU is halted (use the memory/register view of your debugger and refresh the view). Alternatively, if the TCPWM is used to output a PWM signal, you can observe the result at the pin.

 

0 Likes
378 Views