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Frequently Asked Questions about I2C lines - KBA85348

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Frequently Asked Questions about I2C lines - KBA85348

Version: *B

Translation - Japanese: I2C 信号線に関するよくある質問 - KBA85348 - Community Translated (JA)

AN50987 gives an overview of the I2C standard and explains how PSoC®1 devices handle I2C communications. The following listed some of the most frequently asked questions about I2C for PSoC®1 devices.

Question 1: Why resistors of 330 ohm are required on I2C lines?

Answer: The series resistors of 330 ohm added on the I2C lines is to increase the RF noise immunity.

The resistor along with the pin capacitance forms a low pass filter and filters out any high frequency signals which may get coupled to the I2C lines.

Question 2: What is the range of pull-up resistor on I2C lines?

Answer: The bus capacitance which is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of Rp (Poll – up resistors) due to the I2C specified rise time (rise time of both SDA and SCL signals). The supply voltage limits the minimum value of resistor Rp due to the specified minimum sink current of 3 mA for Standard-mode and Fast-mode, or 20 mA for Fast-mode Plus. The equivalent formula of Rp-max and Rp-min list as following:

⇨ Rp(max) = tr / 0.8473 × Cb

⇨ Rp(min) = (VDD – VOL(max)) / IOL

  • tr - Rise time of both SDA and SCL signals, it specified in I2C Spec
  • Cb - Estimated bus capacitance
  • VDD - Supply voltage of I2C bus, it specified in I2C Spec
  • IOL - Minimum sink current of I2C bus, it specified in I2C Spec
  • VOL(max) - LOW-level output voltage, it specified in I2C Spec

Question 3: What is the maximum communication speed of an I2C bus at 3.3V for PSoC®1? Can I run the I2C at 400 kHz at 3.3V?

Answer: The I2C Clock parameter specifies the required clock speed at which to run the I2C interface. Three clock rates are available:

50K Standard

100K Standard

400K Fast

The 400 kHz I2C speed is only possible if the IMO (SysClk) is at 24 MHz. The maximum communication speed of the I2C bus does not depend on the voltage setting. It is dependent on the SysClk setting. So, if the SysClk is set to 24 MHz in the global resources, you can run the I2C at a maximum speed of 400 kHz.

The clock speed selection in an I2C user module assumes that the SysClk is 24 MHz. If the Sysclk is set to SLIMO mode (6 MHz SysClk) in the global resources, the I2C speed set in the user module parameter will also scale down accordingly. For example, if SysClk is 6 MHz, the possible clock speeds are 12.5K, 25K, and 100K. SysClk is separated from the CPU clock.

Question 4: How does the I2C clock speed affect the duration of clock stretching introduced by the I2C slave?

Answer: Clock stretching is a phenomenon where the I2C slave pulls the SCL line low on the 9th clock of every I2C data transfer (before the ACK stage). The clock is pulled low when the CPU is processing the I2C interrupt to evaluate either the address or process a data received from Master or to prepare the next data when Master is reading from the slave.

The time the clock is pull low depends on the time the CPU takes to process the interrupt and hence is dependent on the CPU speed and not the I2C clock speed.

Question 5: What is the worst case duration of clock stretching?

Answer: Clock stretching is a phenomenon where the PSoC I2C slave pulls the SCL line low after the 8th clock of every I2C data/address transfer (before the ACK/NAK stage).

PSoC when configured to act as an I2C slave pulls the SCL line low soon after the reception of an incoming I2C data byte. An interrupt is accompanied with this event and it is inside the ISR of this interrupt that CPU initiates the release of the clock line by writing appropriate ACK/NAK status to I2C control register.

Worst case time for which the clock stretching occurs can be computed from the equation below,


No of enabled interrupts in the project = N (including the I2C ISR)

Clock Stretching Time = (25Cycles * N) * CPU_CLK + (Sum of execution time of N ISR’s)

Note: Execution time of one ISR can be computed by multiplying CPU clock time with number of CPU clock cycles associated with that ISR

Question 6: What are the Rise and Fall time specifications for SCL and SDA lines of I2C communication in PSoC device?

Answer: The PSoC is fully compliant to the Philips I2C bus standard - UM10204: I2C-Bus Specification and User Manual.

The following table shows the rise and fall time specifications for both SCL and SDA lines in Fast mode plus, Full speed and Standard speed of operation.

ParameterStandard mode(100KHz)Fast Mode(400KHz)Fast Mode Plus(1000KHz)Unit
Rise Time(for both SCL and SDA)-100020300-120ns
Fall Time(for both SCL and SDA)-30020×(VDD/5.5V)30020×(VDD/5.5V)120ns
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Last update:
‎Jan 03, 2013 04:12 AM
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