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FM4 Software Consideration for Multiple ADC Units used Simultaneously - KBA227598

FM4 Software Consideration for Multiple ADC Units used Simultaneously - KBA227598

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Author: TakashiM_61           Version: **

Translation - Japanese: タイトル:複数のADCユニットを同時に使用した場合のFM4ソフトウェアの検討- KBA227598- Community Translated (JA)


What is the software consideration to use multiple ADC units in FM4 device simultaneously?


The FM4 device has several types of device, and some FM4 devices have multiple ADC units inside the device. If these multiple ADC units are used simultaneously, it is necessary to synchronize the compare clock phase between multiple ADC units. If the compare clock phase is not synchronized between the multiple ADC units, there is a possibility that a noise is routed to power lines and analog reference voltage, as shown below.


Compare Clock Phase Synchronization

The frequency division ratio can be configured for each ADC unit, and each ADC unit can be run with different clock frequencies. Therefore, it is generally difficult to synchronize clock phase between multiple ADC units.

However, if all ADC units use the same compare clock frequency and perform A/D conversion at same time, the compare clock phase can be synchronized.

This can be achieved by configuring the system bus APB1 clock to the required ADC compare clock, and the clock phase is synchronized between multiple ADC units.

Note that it is necessary to configure the system bus APB1 clock first and then initialize ADC. After this initialization, set the APB1 clock to the required frequency. For more information, refer to the below sample code.

Sample Code

FM4_CRG-->APBC1_PSR = 0x82; // APB1 clock is set with HCLK divided by 4 (example: HCLK=160MHz then 40MHz)

ADC_Initialization();      // Initialize ADC (example: the compare CLK: 40MHz)

// if ADCEN register is set, ADC divider circuit is worked.

FM4_CRG-->APBC1_PSR = 0x80; // Example: APB1 is multiplied by 4 (same as HCLK=160MHz)

Shows the APB1 Prescaler Register (APBC1_PSR) mapping and APB1 bus clock frequency division settings.



Refer to the 32-Bit Microcontroller FM4 Family Peripheral Manual.

Restrictions of Synchronize Implementation using system bus APB1

The synchronize implementation is restricted in conjunction with 1/1, 1/2, 1/4, or 1/8 of HCLK from the system bus APB1 division ratio. For example, if HCLK is 160 MHz, ADC compare clock is 40 MHz or 20 MHz.

Additionally, if slower clock is required for ADC compare clock, it is necessary to adjust the timing (clock phase) by inserting the NOP instructions in code. If HCLK is set with slower frequency, it is necessary to consider a total system level influences because HCLK is the all clock source for system.