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Error correction code (ECC) support in PSoC™ 5LP MCU - KBA233921

Error correction code (ECC) support in PSoC™ 5LP MCU - KBA233921

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Error correction code (ECC) support in PSoC™ 5LP MCU - KBA233921

Version: **

What is an ECC block?

The ECC block is responsible for error detection and correction. For every 8 bytes of firmware memory ECC can correct one bit of data and detect 2 bits of error. One bit of error will be corrected. The flash output is 9 bytes wide with 8 bytes of data and 1 byte of ECC data.

Is it possible to disable/enable ECC?

For devices that support an ECC in the flash, this NVL bit is used to set whether ECC is enabled.
0 – ECC disabled
1 ECC enabled
When ECC is enabled, each row of flash has 256 bytes of data plus an additional 32 bytes for ECC data.

How frequently is the ECC data changed?

ECC data in flash will change every time a write is done to the corresponding flash row. When a flash region is read, the corresponding ECC data will be used for error checking. The error checking is dynamic and happens every time the cache reads from the flash; this means, the comparison is for the latest data written to flash.

In case of a 1-bit error, will the data in flash be corrected?

The correction only occurs in the cache, and the code in flash will not be corrected.

How will I know where the error was detected?

In case of a single-bit error, an error is detected and corrected. A multi-bit error can only be detected and cannot be corrected. The address where the error occurred is stored in CACHE_ECC_CORR register. Note that this address field is valid only when INT_VALID field of this register is set to 1.
Refer to the PSoC™ 5LP registers TRM for more details on these registers.

Can an interrupt be generated in case of an ECC error correction/detection?

Interrupt can be generated on ECC correction by setting INT_ENB bit of CACHE_ECC_CORR register. Interrupt can also be generated on error detection by setting the INT_ENB bit of the CACHE_ECC_ERR register. All interrupt sources within the ECC are passed through a mask condition; then, they are reduced into a single interrupt request to the interrupt controller unit. Refer to the PSoC™ 5LP datasheet for details on the interrupt vector table.

How can I perform a desired task when ECC interrupts occurs? 

In case you want to perform some task when the ECC error occurs, you can do so by using the global signal component and setting the cache interrupt as the interrupt source. The out terminal of the component allows you to connect a cache/ECC signal to an interrupt as shown in the image below. You can then create an interrupt handler to perform the desired task.

Figure 1: Using cache interrupt signal to generate an interrupt



Will the device shut down in case of an ECC error?

The device does not stop working when the interrupt occurs. But it is better to shut down the PSoC™ MCU device if an error occurs and is not correct.