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Error Correcting Code to Detect and Correct Single-Bit Errors – KBA90941

Error Correcting Code to Detect and Correct Single-Bit Errors – KBA90941

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Translation - Japanese: シングルビットエラー検出及び訂正のためのError Correcting Codeについて – KBA90941- Community Translated (JA)

Question: What is error correcting code (ECC)? How does it help in single-bit error detection and correction?


Error correcting codes are algorithms that allow data that is being read to be checked for errors and, when necessary, corrected on-the-fly. In case of an SRAM during a write operation, the error correction algorithm uses bits from the data word to incorporate parity check bits into the final word that will be stored in the internal memory array. These algorithms are superior to conventional parity-checking methods, where the errors are only detected but not corrected. In the case of ECC, whenever the data is read out, parity bits of the stored data are compared with parity bits of the data being read out. If a single-bit error has occurred, the above comparison will reveal this error. Thus, ECC allows for the detection of soft errors at a minimal cost in terms of circuit complexity and memory width. Figure 1 illustrates an ECC implementation.

Figure 1. ECC Implementation

ECC implementation

Hamming code is one of the most popular algorithms for single-bit error detection and correction. Compared to other ECC schemes (for example, Viterbi decoding and Reed-Solomon codes), the Hamming Code circuit is less complex; it consumes the least power and provides the shortest decoding time. A Hamming Code is represented by (n, k), which implies that k-bit data words are mapped to n-bit code-words. The Hamming Code algorithm for single-error correction requires N+1 parity bits for 2^N bits of data.

For more information, refer to the following:

Soft Errors and Their Effect on Semiconductor Devices – KBA90938

Different Ways to Mitigate Soft Errors in Asynchronous SRAMs – KBA90939

ECC Implementation in Cypress’s 65-nm Asynchronous SRAMs – KBA90940

For more details on the ECC feature of Cypress’s 65-nm Asynchronous SRAMs, refer to AN88889 - Mitigating Single-Event Upsets Using Cypress’s 65-nm Asynchronous SRAM.