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Enabling Enhanced High-Performance mode in S25FL-S flash memory – KBA236108

Enabling Enhanced High-Performance mode in S25FL-S flash memory – KBA236108

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Community Translation: Enabling Enhanced High-Performance mode in S25FL-S flash memory(S25FL-S flash memoryでEnhanced High-P...

Version: **

If the flash memory is in read-only mode, a mode bit is used to remove eight read instruction phase clock cycles in continuous read. The High-Performance mode supports this mode bit in the Quad I/O command only. Enhanced High-Performance mode expands this mode bit functionality to broader read commands, which include the QUAD I/O Read, DDR Fast Read, Dual I/O Read, and Dual I/O DDR Read.

Do the following to enable Enhanced High-Performance mode:

  1. Select the device part number that supports Enhanced High-Performance Latency Cycles (EHPLC); see Table 1.
  2. Use the comparison of required mode and dummy cycles in Table 2 and Table 3 to determine the mode and dummy cycles for SDR and DDR Enhanced High-Performance.

The flash memory is ready to be used for desired frequency and can be used just the same as the normal mode bit operation.

For example, consider the ordering information on page 132 of the S25FL512S datasheet (Doc. No. 001-98284); the model number option can be found as follows:

A S25FL512SAGBHBA10 device running at 80-MHz clock speed in Single Data Rate (SDR) is in A = EHPLC, 5 x 5 ball BGA footprint with RESET# and V_IO (Versatile I/O Power Supply) package. This device has 4 mode cycles and 0 dummy cycles in Dual I/O Read command and 2 mode cycles and 4 dummy cycles in Quad I/O Read commands.

Table 1 Model number ordering information of S25FL512S latency type

Package details, RESET# and V_IO support

EHPLC (Enhanced High-Performance Latency Cycles)

HPLC (High-Performance Latency Cycles)

SO footprint

0

9

5x5 ball BGA footprint

2

4

4x6 ball BGA footprint

3

8

SO footprint with RESET#

G

H

SO footprint with RESET# and V_IO

R

Q

5 x 5 ball BGA footprint with RESET# and V_IO

A

7

4 x 6 ball BGA footprint with RESET# and V_IO

B

6

5 x 5 ball BGA footprint with RESET#

C

E

4 x 6 ball BGA footprint with RESET#

D

F

 

Table 2  Mode and dummy cycles differences of latency type in Single Data Rate (SDR)

Frequency (MHz)

LC

Dual I/O Read (BBh, BCh)

Quad I/O Read (EBh, ECh)

   

EHPLC

HPLC

EHPLC

HPLC

   

Mode

Dummy

Mode

Dummy

Mode

Dummy

Mode

Dummy

≤ 50

11

4

0

0

4

2

1

2

1

≤ 80

00

4

0

0

4

2

4

2

4

≤ 90

01

4

1

0

5

2

4

2

4

≤ 104

10

4

2

0

6

2

5

2

5

≤ 133

10

-

-

-

-

-

-

-

-

 

Table 3 Mode and dummy cycles differences of latency type in Double Data Rate (DDR)

Frequency (MHz)

LC

DDR Fast Read (0Dh, 0Eh)

DDR Dual I/O Read (BDh, BEh)

   

EHPLC

HPLC

EHPLC

HPLC

   

Mode

Dummy

Mode

Dummy

Mode

Dummy

Mode

Dummy

≤ 50

11

4

1

0

4

2

2

0

4

≤ 66

00

4

2

0

5

2

4

0

5

≤ 66

01

4

4

0

6

2

5

0

6

≤ 66

10

4

5

0

7

2

6

0

7

≤ 80

00

4

2

-

-

2

4

-

-

≤ 80

01

4

4

-

-

2

5

-

-

≤ 80

10

4

5

-

-

2

6

-

-

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