EiceDRIVER gate driver IC: How to drive high side switch in half-bridge configuration

[Infineon_Team]

Use an isolation technique with the help of a pulse transformer (PT) to solve the problem of floating emitter/source points. Use a 1:1 isolation transformer on the high-side gate supply.

Because the transformer has two windings and therefore two separate grounds, the secondary side ground is connected to the transition or floating emitter point, and gate voltage (e.g., +15V) is referenced to the primary side ground. Because of this isolation, when the reference on the secondary side transits, the effect on the primary side gate voltage is not visible, and therefore, no bootstrap circuit is required. Except for an isolation transformer on the high side, the top and bottom gate drivers remain the same in this configuration.

 Figure 1 Isolated transformer connection for half bridge configuration

This technique is generally preferred when the DC operating voltage is quite high because the isolation technique has a lower size compared to the bulky bootstrap circuit components at this high voltage.

Disadvantages: Leakage inductance is greater which induces the oscillations/ringing in gate voltage. For this reason, PTis not recommended for SiC and GaN devices but could be used for IGBT and even for MOSFETS.

Important considerations while choosing an isolation transformer:

1. Check the volt-time product of core to avoid saturation.
2. The leakage inductance of the transformer should be as low as possible to avoid any oscillations due to high transient gate currents. In addition, the parasitic capacitance (coupling capacitance) between primary and secondary of the transformer should be low to avoid resonance (particularly at rapid duty cycle change) and EMI/EMC.
3. The lower value of leakage inductance is also desirable to reduce the time delay in the gate driver circuit.
4. The creepage and clearance between terminals should be adequate enough for proper operation.
5. If required, the transformer should be qualified for a partial discharge test to cause any flash over between terminals.
6. To avoid core saturation, the duty cycle could be limited up to 50%. Avoid this limitation by choosing additional components like capacitors, resistors, and diodes. These additional components prevent the DC voltage across the winding from saturating it.

 Figure 2 R and C component-based isolation technique circuit diagram

7. Another limitation could be its size because of the large package required for winding isolation and other clearances.
8. The transient immunity should be as per system requirements to avoid any CMTI (generally 10-30KV/µsec) or negative transient oscillations.
9. The rated isolation and short-term isolation (for 1 minute, which is generally 5 KV rms) should be met in transformer specifications. 

Important considerations while designing the PCB layout:

1. Minimize the track length and parasitic capacitance to avoid any unwanted oscillations and ground bouncing.
2. The bootstrap capacitor should be placed close to the driver IC pins.
3. Do not route the low-frequency signal track close to the high-frequency signal track and avoid ground looping to avoid any interference.
4. It has a parasitic capacitance across its terminals and between the primary and secondary sides. If operated at a high frequency, it may lead to interference with nearby signals. Therefore, try to keep your control or sensitive signal and transformer connections parallel and at some distance from each other or route the signals on different PCB layers (if you are using a PCB).

Comparison between pulse transformer and coreless transformer gate driver IC solution.

Figure 3 Size comparison between two technologies

Community Translation: タイトル: EiceDRIVERゲートドライバIC：ハーフブリッジ構成でハイサイドスイッチを駆動する方法 – KBA236410

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