EiceDRIVER™: Recommendations for PCB routing in gate driver boards – KBA237949
Failures may occur in the gate driver (EiceDRIVER™) board because of bad PCB layout even if the circuit is accurate. Use the following general points to improve the performance and reduce failures:
- Keep the track length as short as possible. It is a common source of stray inductance, which leads to EMI or noise. As the length increases, the inductance increases, which may radiate and cause EMI issues. As the width of the track increases, the inductance reduces, which can help limit EMI. Generally, the length-to-width ratio for any track between the gate driver IC and power voltage source should not be more than 3:1.
A common example of undesirable turn-on of device (MOSFET, IGBT, GaN, SiC, and so on ) with long trace (high inductance) is while working in half-bridge driver. The stray inductance causes the voltage to oscillate; a negative voltage can stay for a long time across the Vs pin, which may lead to undesirable turn-on and shoot-through.
- Try to keep the two traces running in the PCB parallel to each other and avoid any cross-over. If two high-frequency signals are present that can interfere, try not to keep them very close. Moreover, ensure that the power and ground traces run over each other (on different layers) to avoid loop area and reduce the impedance. While dealing with the power and ground layers, make sure that no unintended common-mode impedance is formed.
- Try to use SMD components rather than through-hole especially when it comes to RF energy, because SMD components have lower inductances and allow closer component placement. Moreover, the leads of though-hole components can act as antennas.
- While placing the gate driver IC (GDIC), the best practice is to avoid any trace running below the IC, either on the same plane or on a different plane. In an isolated GDIC, this point is also valid from an isolation point of view because if any trace (let’s say the ground layer, which is non-floating) is kept, the isolation between the secondary and primary sides may be compromised. However, even in non-isolated GDIC, it is recommended to do so to avoid any crosstalk or noise because of the noise problem from input and output pins, which can propagate because of the area covered by the connection traces, which form an antenna.
- Try to keep any decoupling capacitor connection (for example, across VCC and GND pins) as small as possible to avoid any ringing (i.e., dip or swell in voltage).
- In an isolated gate driver IC, specifically while using a transformer, it has some parasitic capacitance across its terminals and between the primary and secondary sides. If you operate it at high frequency, it may cause interference with nearby signals. Therefore, try to keep your gate driver and transformer connections parallel and at some distance from each other, or route the signals on different PCB layers (if you are using a PCB).
- Either ground or pull up any unused pins to avoid maloperation. For example, depending on the function of the input and output pins, a few unused pins can be gounded and some pins can be pulled up.
- Dissipating the heat properly from any SMD GDIC is very important, and for that, proper cooling is required. If power dissipation is greater and it needs a cooling arrangement, first calculate the power loss and heat dissipation, and depending on that, choose what copper area is needed for heat dissipation. Even after providing the copper area, if the temperature increases, you can provide some air vents in the copper area of the PCB for better heat convection. There are other options, such as thermal pads, that can be used for the application; however, they act as thermal insulators as well. Therefore, if you opt for this, check the compatibility.
- While dealing with via holes in the PCB, make sure that the routing is done properly; otherwise, they break up the layer or plane and either increase the loop area or form unwanted cross-overs from other signals that are routed nearby. This is a common recommendation while dealing with multilayer boards.
For more details, see the following: