EiceDRIVER™ 1ED44173N01B: Gate driver FAQs
Low-side driver IC query
How do I calculate the fault clearing time for 1ED44173N01B gate driver IC?
Use the following equation to calculate the fault-clearing time:
Figure1 1ED44XX fault connection diagram
For example, if =10 kΩ, = 1 nF, = 5 V, and = 2.1 V (typical)
Then as per the calculation the fault clearing time is = 5.4 µs.
Half bridge driver IC query
How do I calculate pull-up and pull-down resistance using data sheet values?
In few gate driver IC data sheets (EiceDRIVER™ IC), such as the IR2011S data sheet, the pull-up and pull-down resistor values are not directly provided. In such cases, determine the values using the data sheet parameters like VL0, Io-, and VHO, Io+. Use the following equation for calculation.
What are the recommendations to measure signals with respect to the floating signals?
Testing a high-side signal, such as HO-VS or VB-VS is challenging because these nodes are floating.
The best way to test them is to use a high-voltage differential voltage probe with high CMRR at high frequency (such as the Tektronix TIVM IsoVu probe or the Lecroy HVFO probe).
How do I understand the use of EN/FLT pin of the 2EDL23I06PJ and 2EDL23N06PJ driver ICs?
The EN/FLT pin is an open drain configuration, which offers two functions on one pin.
- Enable input (EN)
- Fault output (FLT)
For both functions to work properly, the pin should have an open drain output, which in turn requires the external pull-up resistor to achieve a logic high state. When a failure occurs, the EN is pulled down, which disables the IC, and when the IC recovers, the internal open drain is switched OFF. If externally, the EN is connected to a resistor pull-up, the EN pin may return automatically to a high level by pulling up the internal drain voltage.
Figure 2 2EDxx fault pin connection
Single channel isolated driver IC query
How do I compare the PWM logic voltage level with the VCC1 supply?
In few gate driver ICs, the PWM logic level is scaled up as per the input threshold. For example, in 1EDI20I12AF, the gate driver detects a logic high and a logic low for any input voltage level exceeding 70% of the VCC1 and falling below 30% of VCC1, respectively.
Figure3 PWM logic parameter