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Differential Clock Requirements for HyperBus™ Products – KBA219878

Differential Clock Requirements for HyperBus™ Products – KBA219878

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Translation - Japanese: HyperBus™製品の差動クロック要件 – KBA219878 - Community Translated (JA)


What are the requirements for differential clocks on HyperBus?


Cypress HyperBus family of products, including HyperRAM and HyperFlash, are high-speed low-pin-count devices. In 1.8-V devices, such as S26KSxxxS HyperFlash, they require a pair of differential clock signals, CK and CK#. In 3.0-V devices, only a single-ended clock, CK, is required.

You may be familiar with differential clock requirements in DDR SDRAM memories. However, the requirements for the differential clocks in HyperBus are different from DDR DRAM products.

To manage the higher data rates, DDR SDRAM often uses Stub Series Terminated Logic (SSTL) for its differential clock signals. Two commonly used termination schemes of SSTL are:

  • Single parallel terminated output load with or without series resistors (Class I, as stated in JESD8-15a)
  • Double parallel terminated output load with or without series resistors (Class II, as stated in JESD8-15a)

In Cypress HyperBus devices, there is no requirement to use SSTL for differential clocks. Users can just use simple CMOS-compatible I/O signals to communicate with HyperBus devices, including the differential clocks.

Some considerations should be noted when designing the PCB layout for the differential clocks in HyperRAM or HyperFlash:

  1. CK and CK# should be routed in a coplanar fashion while maintaining the single-ended impedance of 50 ohms and differential impedance of 100 ohms (nominal value).
  2. CK and CK# should be broken out in a coupled fashion, i.e., maintain the trace width and trace spacing between these signals identical throughout the breakout region as much as possible (this is true when they exit the breakout area). In addition, shield the clocks with VSS guard traces if possible.

Cypress provides IBIS models of HyperBus memories for customers who want to run simulations to check signal integrity. The mo dels are available on this page: http://www.cypress.com/products/hyperbus-memory . Click on the Design Models tab to download.

Cypress also provides design guidelines on board layout and other aspects. Check out these Application Notes on this page: http://www.cypress.com/search/all?f[0]=meta_type%3Atechnical_documents&f[1]=field_related_products%3...