Differences in integration of HSSL peripheral module into AURIX™ families – KBA235396
The integration of the HSSL module peripheral into various AURIX™ families (TC2x, TC3x and TC4x) differs in the following aspects:
- Dual-instance support (only supported for some TC3x and TC4x derivatives; limited support for TC2x)
- Multi-slave support (only supported for TC3x and TC4x; not supported for TC2x)
- Peripheral PLL of TC3x and TC4x replaces HSCT PLL and ERAY PLL of TC2x
- Different dividers to derive the HSSL module’s peripheral clock from the peripheral PLL (only relevant for TC3x and TC4x)
1 Dual instance support (supported for some of the TC3x, TC4x derivatives and limited support for TC2x)
In TC3x and TC4x families, there are AURIX™ derivatives available, which come with up to two HSSL instances implemented within one device. This allows to connect one slave device to each instance available within one master device. Optionally, the two instances available within one slave device can be connected to the two instances available within one master device.
- Use two instances to double the available baud rate through HSSL when interconnecting two devices.
- On the HSSL layer, each instance available within a device can be operated independently and in parallel, with a maximum high-speed baud rate of 320 MBaud.
- Connecting the single instances of two slave devices to the two instances of one master allows full high-speed and parallel operation with a baud rate of 320 MBaud. Always consider the option of using dual-instance operation to overcome feature and ease-of-use limitations of multi-slave operation; see Multi slave support.
- Even when there is no dual-instance derivative available in the TC2x device family, still the single instance of a TC2x device can be connected as a slave device to one of the instances of a dual-instance master device (i.e., TC3x or TC4x).
Dual-instance derivatives are available only in TC3x and TC4x families. No dual-instance derivatives are available in the TC2x family.
2 Multi-slave support (only supported for TC3x TC4x; not supported in TC2x)
Multi-slave support is available only in TC3x and TC4x devices and allows to interconnect up to four AURIX™ devices using HSSL. One AURIX™ device operates as a master device and up to three devices operate as slave devices.
Multi-slave mode usage is different and partly limited compared to single-slave mode:
- On the HSCT layer, each slave filters all arriving packets only for its own packets before internally forwarding them to the HSSL layer.
- The master is responsible to activate or deactivate the slave TX with interface commands.
- Only one slave TX must be active at a time, and can respond to the master’s requests or send a request to the master.
- The Ping interface command is not supported in multi-slave mode.
- Internal termination resistor is not supported.
Depending on the number of slaves connected, the maximum baud rate for high speed is limited as follows:
Number of slaves
Maximum high-speed baud rate
Note: Because of multi-slave mode’s feature and ease-of-use limitations, always consider the option of using
dual-instance implementation instead; see Dual instance support.
Multi-slave mode is supported only by HSSL module peripherals implemented in TC3x and TC4x families. Not supported in TC2x family.
3 Peripheral PLL of TC3x and TC4x replaces HSCT PLL and ERAY PLL of TC2x
In TC2x derivates, the HSSL peripheral module is supplied by the clock coming from its independent HSCT PLL. On the input side, this independent HSCT PLL is either supplied from the oscillator (master device) or from the clock provided on SysClk input (slave device). The SysClk input is used exclusively for providing the reference clock for the HSCT PLL. As a consequence, other modules’ clocks (mostly derived from ERAY PLL) in TC2x derivatives do not depend on the availability of the SysClk input.
3.2 TC3x and TC4x
In TC3x and TC4x derivatives, the HSSL peripheral module is supplied by the clock coming from the Peripheral PLL. The Peripheral PLL is also used to supply a wide range of other peripherals inside those derivatives. In slave devices, the Peripheral PLL and the System PLL are both supplied by the SysClk input. This results in the complete clock of all peripherals and all TriCore™ subsystems being supplied by the SysClk input clock (provided by the HSSL master device).
3.3 Design considerations
- When designing the start-up and power-down behavior of the overall system, system architectures that include TC3x and TC4x slave devices must consider that the clock for all slave devices is provided by the master device through the SysClk input.
- Keep in mind that in system architectures that include TC3x and TC4x slave devices, any failure on the master’s clock provision will propagate to the slave device.
- In the TC2x family, the HSSL peripheral’s module clock is sourced by its HSCT PLL. In TC2x slave devices, only the HSCT PLL is sourced from the SysClk input.
- In TC3x and TC4x families, the HSSL peripheral’s module clock is sourced by the Peripheral PLL of the device. In TC3x, TC4x slave devices, the complete clock system of the whole device is sourced by the clock coming from the SysClk input.
4 Different dividers to derive HSSL module’s peripheral clock from Peripheral PLL (only relevant for TC3x and TC4x)
Not applicable. There is no Peripheral PLL in TC2x. The Peripheral PLL of TC3x and TC4x replaces the HSCT PLL and ERAY PLL of TC2x.
The Peripheral PLL output clock frequency is divided by two before it is used to supply the module clock (fHSCT) to the HSSL peripheral module.
For the nominal use case of fHSCT = 320 MHz, which allows maximum high-speed baud rate of 320 MBaud, the frequency of the Peripheral PLL must operate with 640 MHz.
The Peripheral PLL output clock frequency is divided by 2.5 before it is used to supply the clock for the HSSL peripheral module.
For the nominal use case of fHSCT = 320 MHz, which allows maximum high-speed baud rate of 320 MBaud, the frequency of the Peripheral PLL must operate with 800 MHz.
- To support maximum baud rate, set the Peripheral PLL clock output to 640 MHz on TC3x using a 20-MHz or 40-MHz input frequency. As a consequence, the maximum HSSL baud rate is reached with 20-MHz or 40-MHz crystal/SysClk input.
- To support the maximum baud rate, set the Peripheral PLL clock output to 800 MHz on TC4x using a 20-MHz, 25-MHz, 40-MHz, or 50-MHz input frequency. As a consequence, the maximum baud rate can be reached with 20-MHz, 25-MHz, 40-MHz, or 50-MHz crystal/SysClk input.
- Keep in mind that other peripheral modules are also operated at the same Peripheral PLL clock output frequency.
- TC2x family: Not applicable.
- TC3x family: fHSCT is sourced by the Peripheral PLL clock divided by two; (fSysClk = 20 MHz or 40 MHz).
- TC4x family: fHSCT is sourced by the Peripheral PLL clock divided by 2.5; (fSysClk = 20 MHz, 25 MHz, 40 MHz or 50 MHz).