Design recommendations for Gate Driver and CoolSiC™ MOSFET
- The interconnection between gate driver and the CoolSiC™ MOSFET device should have a minimum inductance and mutual inductance with the load circuit. This means the driver should be located as close as possible to the device.
- Capacitive coupling from the drain to the driver and to other parts of the circuit has to be minimized. Overlapping of this potential with other signals has to be avoided wherever possible.
- The switching behavior of Infineon's CoolSiC™ MOSFET is highly controllable via the gate resistor. Therefore, the gate resistor should be selected for an optimum trade-off between minimizing switching loss vs. overshoots and oscillations.