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Design of external passive components and layout measures to reduce Vgs ringing – KBA236326

Design of external passive components and layout measures to reduce Vgs ringing – KBA236326

Infineon_Team
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Community Translation:   タイトル: Vgs リンギングを低減するための外付け受動部品の設計とレイアウト対策 – KBA236326

Version: **

1. Cause and impact of gate voltage oscillations

Ringing or parasitic oscillations on the gate voltage can cause unwanted behavior in the MOSFET, such as false turn-on, higher power losses, and also damage to the device.

1.1 Source of oscillations on the gate terminal

  • Resonant circuit: Formed by parasitic inductance on the gate path and the input capacitances (Cgd & Cgs) of the switching device.
  • dv/dt feedback from miller capacitor: Vds oscillations during turnoff that are coupled to gate via Cgd.
  • di/dt feedback from source stray inductance: High di/dt of the drain current can result in oscillations on the source pin because of parasitic inductance on the source terminal which reflects on the gate voltage.

1.2  How the gate ringing can cause damage to the device?

During switching, the MOSFET is not fully homogenous. Because of the resistance/capacitance network, there will be a short delay in the switching of the trenches farther away from the gate pad. This delay is uncritical if the switch-on process is normal i.e., the gate voltage is clean without any high-frequency oscillation.

With the oscillations on the gate signal however, the gate voltage periodically drops below the Miller plateau voltage and the trenches far away from the gate pad do not switch on properly, as they do not reach the gate voltage above the Miller plateau. Drain to source current will be forced into the partly turned-on trenches near the gate pad and source pad. This uneven distribution slowly leads to damage of the device because of local heating.

2.Methods to dampen the gate voltage oscillations

There are two ways to dampen these oscillations.

  1. Minimize the parasitics
  2. Use of external passive components

2.1 Minimize the parasitics

  • Minimize the parasitic inductance on the gate and source path
    • Using shorter and wider traces from gate driver output to device terminals
    • Maintaining a low cross-sectional area of the gate loop
    • Avoiding the use of via’s on the gate drive path by routing both to and return current paths on the same layer
  • Minimize the parasitic capacitance between gate and drain by decoupling the layout

Infineon_Team_0-1665128073667.png

Figure 1  Parasitic elements in the gate drive loop of MOSFET

2.2 Use of external passive circuits

2.2.1 RC snubber across the switching device

Use of RC snubber circuit across the switching device. For example, drain to source of a MOSFET will dampen the Vds spikes. This shall protect the device from overshoots and reduce the oscillations due to feedback via Cgd.

2.2.2 Sizing of external gate resistor

Rg is mainly responsible for damping the ringing caused due to gate path parasitics.

  1. Higher value Rg will overdamp the ringing but result in higher switching loss whereas lower value Rg, will enable fast switching but under damp the oscillations, which also might result in Vds overshoots. 
  2. Therefore, it is advised to choose Rg such that Q lies between 0.5 (critically damped) to 1(underdamped) . Following is the practical approach that most designers follow to obtain the value of Rg.
    a. Measure the gate oscillation frequency(fr) without connecting any resistor between the driver and the switch
    b. Obtain the parasitic inductance value as follows:
    Infineon_Team_3-1665128223920.png
    c. Calculate the Rg value which can provide the Q factor between 0.5 to 1
    Infineon_Team_2-1665128185531.png

     


    i)          Q = 0.5: No gate oscillations. But Rg value will be higher, which can cause higher switching loss and also increase the chances of parasitic turn-on due to high dv/dt.
    ii)             Q=1: Rg value will be lower, therefore lower switching loss. But measures are to be implemented to reduce gate oscillation, limit noise, and protection against Vds overshoot. However, if you are using a gate driver, then the minimum Rg value should be such that it does not violate the peak source and sink current limits of the driver and the power dissipation capability of the driver. If turn on and turn off path are the same, then,
    Infineon_Team_1-1665128132207.png

For example: If the gate voltage swings between +15 V to -8 V, and driver current limits are 4A_source/2A_sink, then minimum Rg = 11.5 ohm.

Therefore, Rg_ext = 11.5 – Rg_int – Rds_on_drv  or

Rg_ext = 11.5 – Rg_int – Rds_off_drv, whichever is higher.
              iii)          Therefore, Rg has to be tuned between these two values.

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