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Debugging when DMA Flags do not Work as Expected while Reading Data from FX3 – KBA230545

Debugging when DMA Flags do not Work as Expected while Reading Data from FX3 – KBA230545

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Author : HemanthR_06          Version: **

Translation - Japanese: FX3からのデータの読み取り中にDMAフラグが期待どおりに機能しない場合のデバッグ – BA230545 - Community Translated (JA)

Question: DMA flags do not work as expected while reading data from FX3? How do I troubleshoot?

Answer: As per the application note AN65974, FLAG C is the DMA READY flag dedicated to Thread 3 and FLAG D is the DMA Watermark flag dedicated to Thread 3. These flags are used for flow control.

If these flags do not work as per the read sequence mentioned in section 5.1 of AN65974, do the following preliminary checks:

  • Probe the SLCS, SLRD, SLOE signals to make sure that they are as per section 5.1 of AN65974.
  • Make sure that the address lines A0:A1 are properly driven and is addressing the correct socket. Flags show unexpected behavior when address lines are not properly driven, as discussed in this thread.
  • Make sure that before transferring data to FPGA/Master through FX3, both flags, FLAG C and FLAG D, are low. The DMA_READY flag starts indicating the status of the DMA buffer only when the host has started transferring data to FX3. The partial flag is observed to reflect the status of the buffers only after one full DMA buffer is read out. So, when the state machine starts, the partial flag cannot be monitored to know the empty status of the buffers.
  • Check whether the host streams Bulk OUT packets (1024 bytes for USB 3.0. and 512 bytes for USB 2.0) from the host when the FPGA state machine, provided with AN65974, is used to read full packets from FX3.
  • If the FPGA Master mode state machine provided with AN65974 is used, check whether the appropriate transfer mode is selected. For example, if slaveFIFO2b.v is used from the fx3_slaveFIFO2b_xilinx folder provided with AN65974, the transfer mode should be STREAM_OUT, that is, by setting mode = STREAM_OUT.
  • Check if the clock from FPGA/Master is stable and connected to FX3’s PCLK correctly.
  • Check if the STREAM_IN_OUT macro is enabled in the firmware provided AN65974.