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Debugging DMA Registers in PSoC 3 and PSoC 5 – KBA226876

Debugging DMA Registers in PSoC 3 and PSoC 5 – KBA226876

50 questions asked 10 questions asked 5 questions asked

Author: JeetendraA_51            Version: **

Translation - Japanese: PSoC 3およびPSoC 5でのDMAレジスタのデバッグ - KBA224514 - Community Translated (JA)


What should be done to view the intermediate values of a DMA channel, for example the transfer count, when a DMA transfer is under progress in PSoC® 3 and PSoC 5?


If your DMA channel number is x and preserve TD is enabled, then PHUB_TDMEMx_ORIG_TD0 will be reserved for DMAC’s private use. So, the PHUB_TDMEM register with the channel number will hold the data temporarily when the TD is being executed. Instead of processing the original TDs in place, DMAC will copy the original TDs to this separate working area and process them there.

For example, if the channel number for the DMA channel is zero, and preserve TD is enabled, then the working set of registers will be PHUB_TDMEM0_ORIG_TD0. The xfrcnt[11:0] of the PHUB_TDMEM0_ORIG_TD0  register will hold the intermediate value. So, if you read this value ( xfrcnt -> [11:0]), you will get the intermediate count. The channel number of the DMA channel can be found from cydwr tab of PSoC Creator™ after a successful build.