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Considerations for Interrupt Nesting with NVIC in FM0+, FM3, and FM4 - KBA228323


Considerations for Interrupt Nesting with NVIC in FM0+, FM3, and FM4 - KBA228323

Author: TakashiM_61           Version: **

Translation - Japanese: FM0+、FM3、およびFM4のNVICでの割り込みネスティングに関する考慮事項 - KBA228323 - Community Translated (JA)

The Arm® core in FM0+, FM3, and FM4 series MCUs has a Nested Vectored Interrupt Controller (NVIC).

Refer to Chapters 7-2 to 7-4 of the 32-bit Microcontroller FM3 Family Peripheral Manual.

When an interrupt is being handled, if another interrupt happens with a lower priority than the interrupt being handled currently, the lower-priority interrupt request is kept pending inside the NVIC. As the subsequent process, the highest-priority pending interrupt will be handled after the previous interrupt handling is completed.

However, if the next interrupt request during the interrupt service routine (ISR) triggered by the previous interrupt does not require to be handled, both the interrupt request from peripheral functions and the interrupt request which was pending inside NVIC must be cleared.

For example, two bytes of serial data is served in one ISR as follows:


The 2nd interrupt needs to be cancelled because the 2nd byte data has been already received in the 1st ISR triggered by the 1st interrupt.

When the 2nd interrupt is cancelled in the 1st ISR, only the 2nd interrupt request from peripheral functions is cleared. In this case, because the 2nd interrupt request has been pending in NVIC, this pending 2nd interrupt request triggers an unexpected ISR after 1st ISR is completed.


Another solution to be avoid the unexpected interrupt is to mask the interrupt at the beginning of the ISR, instead of in the NVIC, as shown in the following figure.


Even though these example describe a case of interrupts from serial data communication, the solutions are applicable for interrupt requests from other peripheral functions also.

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