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Considerations for Interrupt Nesting with NVIC in FM0+, FM3, and FM4 (KA-03427)

Considerations for Interrupt Nesting with NVIC in FM0+, FM3, and FM4 (KA-03427)

BinduPriya_G
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Considerations for Interrupt Nesting with NVIC in FM0+, FM3, and FM4 (KA-03427)

Community Translation: FM0+、FM3およびFM4のNVICでの割り込みネスティングに関する考慮事項(KA-03427)

The Arm® core in FM0+, FM3, and FM4 series MCUs has a Nested Vectored Interrupt Controller (NVIC).
While an interrupt is being handled, if another interrupt happens with a lower priority than the interrupt being handled currently, the lower-priority interrupt request is kept pending inside the NVIC. As the subsequent process, the highest-priority pending interrupt will be handled after the previous interrupt handling is completed.
However, if the next interrupt request during the interrupt service routine (ISR) triggered by the previous interrupt does not require handling, both the interrupt request from peripheral functions and the interrupt request which was pending inside NVIC must be cleared. More here.

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