The WDT cannot be cleared in Sleep or DeepSleep power modes. To clear the WDT, the CPU needs to wakes up.
In Sleep or DeepSleep power modes, the CPU subsystem is powered-down. The watchdog counter can send a WDT WARN ACTION interrupt request to the wakeup interrupt controller (WIC), then WIC wakes up the CPU.
After wakeup, the CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware. For more details, refer to the Watchdog Timer (WDT) section in the Architecture Technical Reference Manual.
Note: This applies to the following series of TRAVEO™ II MCUs:
- CYT2 Series
- CYT3 Series
- CYT4 Series
