Choose the right EZ-PD™ PMG1 MCU for your application requirement - KBA232687

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Community Translation: アプリケーションの要件に適したEZ-PD™ PMG1 MCUの選択 - KBA232687-Community translated (JA)

Version: *B

EZ-PD^TM PMG1 (Power Delivery Microcontroller Gen1) is a family of high-voltage USB-C power delivery (PD) microcontrollers. PMG1 can be employed in any embedded system that provides/consumes power to/from a high-voltage USB-C PD port and leverages the microcontroller to provide additional control capability.

These chips include an Arm^® Cortex^® – M0/M0+ CPU and USB PD controller along with analog and digital peripherals.

The PMG1 family offers four chips with unique features. The following table presents the notable differences between the variants of PMG1 and will assist you in selecting the appropriate PMG1 MCU. For a detailed look on the differences between the chips, see the datasheets (https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/usb-c-and...)

Subsystem or range	Item	PMG1-S0	PMG1-S1	PMG1-S2	PMG1-S3
CPU and memory sub-system	Core	Arm® Cortex®-M0	Arm® Cortex®-M0	Arm® Cortex®-M0	Arm® Cortex®-M0+
	Maximum frequency (MHz)	48	48	48	48
	Flash (KB)	64	128	128	256
	SRAM (KB)	8	12	8	32
Power Delivery	Power Delivery ports	1	1	1	1 port for 48-QFN 2 ports for 97-BGA
	Role	Sink	DRP	DRP	DRP
	MOSFET gate drivers	2x PFET	2x PFET	2x NFET	Flexible 2x NFET
	Fault protections	VBUS OVP and UVP	VBUS OVP, UVP and OCP. SCP and RCP (for source configuration only)	VBUS OVP, UVP and OCP	VBUS OVP, UVP and OCP. SCP and RCP (for source configuration only)
USB	Integrated Full Speed USB 2.0 device with Billboard class support	No	No	Yes	Yes
Voltage range	Supply (V)	VDDD (2.7–5.5) VBUS (4–21.5)	VSYS (2.75–5.5) VBUS (4–21.5)	VSYS (2.7–5.5) VBUS (4–21.5)	VSYS (2.8–5.5) VBUS (4–28)
	IO (V)	1.71–5.5	1.71–5.5	1.71–5.5	1.71–5.5
Digital	SCB (configurable as I2C/UART/SPI)	2	4	4	7 for 48-QFN (out of which only 5 can be configured as SPI and UART) 8 for 97-BGA
	TCPWM block (configurable as timer/ counter, pulse width modulator or quadrature decoder)	4	2	4	7 for 48-QFN 8 for 97-BGA
	Hardware authentication block (Crypto)	No	No	Yes (AES-128/192/256, SHA1, SHA2-224, SHA2-256, PRNG10, CRC)	Yes (AES-128, SHA2-256, TRNG, vector unit)
Analog	ADC	2x 8-bit SAR	1x 8-bit SAR	2x 8-bit SAR	2x 8-bit SAR 1x 12-bit SAR
	On-chip temperature sensor	Yes	Yes	Yes	Yes
Direct Memory Access (DMA)	DMA	No	No	No	Yes
GPIO	Max # of I/O	12 (10+2 OVT)	17 (15+2 OVT)	20 (18+2 OVT)	26 (24+2 OVT) for 48-QFN 50 (48+2 OVT) for 97-BGA
Charging standard	Charging source	–	Battery Charging (BC) 1.2, AC	BC 1.2, AC	BC 1.2, AC, Adaptive Fast Charging (AFC) and Quick Charge (QC) 3.0
	Charging sink	BC 1.2, Apple Charging (AC)	BC 1.2, AC	BC 1.2, AC	BC 1.2, AC
ESD protection	ESD protection	Yes (Up-to ± 8-kV contact discharge, up-to ±15-kV air discharge, human body model (HBM) and charged device model (CDM))	Yes (HBM and CDM)	Yes (Up to ± 8-kV contact discharge, up to ±15-kV air discharge,HBM and CDM)	Yes (HBM and CDM)
Packages	Package options	24-QFN (4 x 4 mm, 0.5-mm pitch)	40-QFN (6 x 6 mm, 0.5-mm pitch)	40-QFN (6 x 6 mm, 0.5-mm pitch) 42-CSP (2.63 x 3.18 mm, 0.4-mm pitch)	48-QFN (6 x 6 mm, 0.5-mm pitch) 97-BGA (6 x 6 mm, 0.5-mm and 0.65-mm pitch)