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Can VCC, VI/O & RESET signals have a stepped rising edge during power-on or Vcc ramp-up for the S29GL-P? - KBA203392

Can VCC, VI/O & RESET signals have a stepped rising edge during power-on or Vcc ramp-up for the S29GL-P? - KBA203392

Anonymous
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JP Translation:S29GL-PのVCC、VI/O、RESET信号は、電源投入時やVccランプアップ時にステップ状の立ち上がりエッジを持つことができますか? - KBA203392

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Question:

Can VCC, VI/O & RESET signals have a stepped rising edge during power-on or Vcc ramp-up for the S29GL-P?

 

Answer:

Regarding the S29GL-P, during Power-On, VCC should rise monotonically (no step on rising edge) and must remain greater than VLKO during all reset operations. VIO can either be tied to VCC or can be driven to a different voltage level. In the latter case, VIO must exceed VIO_MIN before RESET# is negated and must be maintained between VIO_MIN and VCC +100 mV.

During VCC ramp-up, RESET# must be asserted (low). From the period in time when VCC exceeds VCC_MIN, (RESET# must remain asserted for a period of tVCS) prior to negation (see Figure 3.1 in app note).

Control signal transitions can be initiated tRH following RESET# negation. URL to "Reset Voltage and Timing Requirements for MirrorBit® Flash" app note: 

http://www.spansion.com/Support/Application%20Notes/mirrorbit_reset_an.pdf

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