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CYW20719 and CYW20735 Analog to Digital Converter(ADC)

CYW20719 and CYW20735 Analog to Digital Converter(ADC)

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The Analog to Digital Converter (ADC) block in CYW20719 and CYW20735 is a single-ended switched-cap sigma-delta ADC with 12 bits for Audio* measurements and 10 bits for DC measurements. The ADC has 32 DC input channels including 28 GPIO inputs.

The following pins can be programmed as ADC inputs in CYW20719 QFN40:

     P0, P1, P8–P19, P21–P23, P28–P38.

The following pins can be programmed as ADC inputs in CYW20735 QFN60:

      P0-P14, P16, P26-29, P32,P34,P38

For Audio* applications, the ADC uses a Programmable-Gain Amplifier (PGA) to control the gain.

The CYW20719 and CYW20735 supports two modes of operation: DC measurement mode and Audio mode*. Referefer to the datasheet for more details on supply voltage.

  *Note: The Audio mode (micn and micp pins) is not available in the 40 pin QFN package of the CYW20719.

1.1.  ADC Block Diagram


Figure 1: Block Diagram of CYW20719's ADC

1.2.  DC Measurement Mode

The DC Measurement mode refers to single-ended voltage measurement on an input pin referenced to ADC ground. From the ADC’s block diagram, 28 GPIO channels, VDDIO, VDDC, ADC_BGREF, and ADC_REFGND are multiplexed and fed into the switched-cap sigma-delta ADC.

The wiced_hal_adc_set_power() API allows the program to power up or power down the ADC.

The wiced_hal_adc_init() API initiates the necessary registers required for the ADC operation. The ADC needs to be initialized if the ADC has been powered down in specific low power modes.

2. ADC Output Data and Clock Timing

The ADC clock input is 24 MHz which is divided internally in the ADC hardware to operate at 12 MHz. The typical conversion rate is 100 kHz and the minimum conversion rate is 50 kHz for static measurements of the ADC. The practical time for reading DC voltages after ADC initialization is approximately 150 microseconds. Similarly, the practical time for reading DC raw samples from the ADC is approximately 50 microseconds. This conversion rate roughly translates to a range in between 16ksps and 20ksps(kilo samples per second). This reduction in conversion rate is because the firmware does filtering and averaging of sampled values for better accuracy.

3. ADC Input MUX Clocking in DC Measurement Mode

The ADC requires up to 2 microseconds to settle after switching of the DC input channels. It takes approximately 20 microseconds for the ADC REF to settle after powering up the ADC. The ADC DC input MUX should be held constant for 10 microseconds to 20 microseconds until the DC measurement is finished. This is taken care internally by the APIs. The ADC_DC_MUX_clk is the timing clock on the digital side to synchronize the DC input channel switching and measurement.


Figure 2: Timing Diagram of ADC

4. ADC Gain Calculation

The wiced_hal_adc_read_voltage() API allows the program to read the analog voltage from the ADC. The ADC must be initialized before reading the ADC voltage or else the function call will return 0. All read function calls to ADC registers are blocking. The ADC input and ADC output gain relation in the DC measurement mode can vary due to the following parameters:

  1. When the ADC input range is set to 0 to 1.8 V mode by calling wiced_hal_adc_set_input_range(ADC_RANGE_0_1P8V).
  2. When the ADC input range is set to 0 to 3.6 V mode by calling wiced_hal_adc_set_input_range(ADC_RANGE_0_3P6V).