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“Asynchronous path(s) exist” warning while using PSoC™ Creator – KBA233877

“Asynchronous path(s) exist” warning while using PSoC™ Creator – KBA233877

Chelladurai
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Version: **

Problem:

PSoC™ 3 MCU, PSoC™ 4 MCU, PSoC™ 5LP MCU, and some of PSoC™ 6 MCU devices have a powerful and flexible programmable digital peripheral system. In addition to a set of fixed function blocks they have universal digital blocks (UDBs) and an extensive signal routing system called the digital system interconnect (DSI).

While using the PSoC™ Creator to create custom designs the "Asynchronous path(s) exist" warning may occur when building the project. This happens when there is a timing difference between the clocking network and the DSI. For example, in the case of fixed function block and UDB interface connection as shown in Figure 1 you might end up getting this warning.

Figure 1: Asynchronous paths between fixed function block and UDB interface

Chelladurai_0-1631614368336.png

 

Context:

For Example, in the Figure 1, a fixed-function Component (Timer_1) and a UDB Component (Counter_1) share a common clock. The Counter_1 Component requires the count input to be synchronous with the clock input. However, the cc output from the Timer_1 Component may not be synchronous with the input clock (clock_1) resulting in this warning.

Solution:

This warning can be resolved by adding a Sync component as shown in Figure 2. When you need to use a signal from one clock domain in another clock domain, you can use the Sync component to line up that signal’s transitions to the clock domain of the destination. In this case, the Sync component is clocked using the same clock as the destination; the Sync component ensures that the count input is synchronized with Clock_1.

Figure 2: Adding the Sync Component

Chelladurai_1-1631614496734.png

 

See the static timing analysis (STA) report for more information on the timing violation. The STA report is available under the Results tab of the Workspace Explorer.

Figure 3: Viewing the STA report

Chelladurai_2-1631614578187.png

 

Figure 4: Timing violation section of the STA report

Chelladurai_3-1631614678505.png
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