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AURIX™ MCU: Time taken to access data from memory – KBA235097

AURIX™ MCU: Time taken to access data from memory – KBA235097

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Community Translation: AURIX™ MCU: メモリからデータにアクセスするのにかかる時間 – KBA235097

Version: **

The user manual has the On Chip Bus Access Times” (related to AURIX™ TC2xx devices) and “Resource Access Times” (related to AURIX™ TC3xx devices) chapters that show access times in CPU clock cycles for multiple memory locations.

These CPU access clock cycles represent the ideal case and can be huge in applications with several accesses on the bus in parallel due to arbitration.

Table 1 gives a hint where code is and could be located; this depends on the application use case.

Table 1 CPU access latency in CPU clock cycles for TC27x (The table is partial example for TC27x)

CPU access mode

CPU clock cycles

Data read access to own Data scratch-pad RAM (DSPR)

0

Data write access to own DSPR

0

Data read access to own or another Program scratch-pad RAM (PSPR)

5

Data write access to own or other PSPR

0

Data read access to other DSPR

5

Data write access to other DSPR

0

 

For more details, see the following sections in the User’s Manual:

  • AURIX™ TC2xx devices: “On-Chip System Buses and Bus Bridges”
  • AURIX™ TC3xx devices: “On-Chip System Connectivity {and Bridges}”

Note: 

This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC2xx series
  • AURIX™ TC3xx series
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