AURIX™ MCU: Synchronize operations between CPU cores - KBA234427
Community Translation: AURIX™ MCU：CPUコア間の同期操作-KBA234427
The TriCore™ and the AURIX™ internal buses support atomic (read-modify-write) instructions and transactions.
Atomic instructions are generally used to implement multi-core primitives such as semaphores and locks/mutexes.
The Interrupt Router also has a Service Request Broadcast feature that can trigger multiple service requests (interrupts) at a time.
However, due to CPU interrupt priorities and Interrupt Router arbitration, SRB interrupts will not trigger at exactly the same time.
See the “Atomic Transfers” section in the user’s manual for more details.
Note: This KBA applies to the following series of AURIX™ MCUs
- AURIX™ TC2xx series
- AURIX™ TC3xx series