AURIX™ MCU: Role of SysClk in HSSL communication architecture - KBA237435
In a typical High Speed Serial Link (HSSL) communication setup, the physical interconnection between the communicating AURIX™ devices consists of:
- Two LVDS pairs for the bi-directional communication.
- Single-ended clock supply from the master device to the slave device, called SysClk.
These signals are shown in Figure 1.
Figure 1 HSSL master/slave communication architecture
Typically, the master device’s common clock source is based on a 20 MHz crystal oscillator and the same clock is provided as a clock source to the slave device. It is common for all AURIX™ TC2xx/TC3xx devices that multiply this clock frequency up to the HSCT module’s clock frequency of 320 MHz. That both devices are now running on exact same frequency, while the phase relationship of the fHSCT within the two devices remains unmatched at the first place.
For a reliable serial to parallel conversion of the incoming bitstream on the receiving side of each device, sampling needs to be done at the center of the eye-width, where the maximum eye-height is given. For this, the phase of the sampling clock fHSCT has to be adjusted to the phase of the incoming bitstream. For this purpose, every HSCT frame carries “fixed sync pattern” at the beginning (See Figure 2).
Figure 2 Fixed sync pattern within HSCT protocol frame
On the receiving side, the incoming bitstream is sampled with multiple (TC2xx: six phases and TC3xx: five phases) phases of the sampling clock. Once the sync pattern is detected, it is then checked within “phase correlator” of HSCT peripheral inside AURIX™, which phase was able to sample the sync pattern the best. This phase of the sampling clock is used to sample the remaining bits (max. HSCT frame size is 313 bit) of the current frame.
The only purpose to supply SysClk from the master device to the slave device is to make sure both devices are running on the same frequency, while the phase relationship is later recovered from the incoming bitstream during operation.
From all this, one could conclude, that each device could also be supplied with its own crystal, only if the frequency of the two crystals are close enough. In practice, matching the frequencies with two separate crystal oscillators is at 50ppm. The difference of 50ppm in both frequencies can lead to a significant phase drift of ~100ps on the last bit (bit #313) of a HSCT frame as follows:
Note: The applicable eye height is 55% of the maximum eye width within the center of the eye as shown in Figure 3.
Figure 3 Phase correlators and eye timings with data rate at 320 Mbps
The deterministic or random jitter caused by the phase drift of two devices running on different frequencies using their own crystal the total jitter exceeds the 55% eye-width. As a consequence, the bit error rate (BER) of 10E-12 as mentioned in TC2xx datasheets or TC3xx datasheets can not be guaranteed for such systems.
Note that for the laboratory or prototype series which are not applying SysClk as intended, the BER deterioration may not be apparent at the first glance. For production series, the BER deterioration may only become apparent after some time of wear and aging.
Infineon has designed and validated the overall system, consisting of two AURIX™ devices, including their peripheral PLLs and the phase correlators @SysClk=20 MHz to reach a BER of 10E-12. This means, that the total jitter of systems applying the SysClk as intended will exceed the 55% eye-width only with a probability low enough to reach a BER of 10E-12 according the TC2xx datasheets or TC3xx datasheets.
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series