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AURIX™ MCU: Primary and secondary monitor latency measurement – KBA235560

AURIX™ MCU: Primary and secondary monitor latency measurement – KBA235560

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The primary monitor operation is based on tracking an analog-to-digital converter (ADC) to measure the supply voltages. It is clocked and the clock cycle value is updated for every power management controller (PMC) for the AURIX™ TC2xx devices and power management system (PMS) for the AURIX™ TC3xx devices. However, the maximum real reaction time for a fast voltage spike is greater because of the tracking ADC nature. See the datasheet for the tMON (Max) parameter value for primary monitor reaction time.

The secondary monitor on AURIX™ MCU is based on a dedicated 8-bit SAR ADC for each channel VDD, VDDP3. Each channel is sampled with a maximum 600 ns period. In addition, there is a 3x spike filter applied. There is a maximum of 1.8 µs for the reaction time of supervisor mode (SVM).

For more details, see the following sections in the User’s manual:

  • “Voltage Monitoring” section in the “System Control Units” chapter for AURIX™ TC2xx device
  • “Supply Voltage Monitoring” section in the "Power Management System (PMS) chapter for AURIX™ TC3xx devices

Note:  This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC2xx series
  • AURIX™ TC3xx series