AURIX™ MCU: Memory protection mechanisms – KBA234558

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Community Translation: AURIX™ MCU: メモリ保護メカニズム（Memory protection mechanisms） – KBA234558

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Question: AURIX™ offers different memory protection mechanisms to support freedom from interference. How do they differ and work?

Answer: There are three protection mechanisms:

• Access enable protection
  • Access enable protection filters peripheral accesses using master tag IDs that masters on the bus have (see On Chip Bus Master TAG Assignments in the following user manuals: )TC2xx: AURIX™ TC29x B-Step 32-Bit Single-Chip Microcontroller User's manual and TC3xx: AURIX™ TC3xx User's manual.
• Bus Memory Protection Unit (MPU)
  • Bus MPU protects incoming accesses to the CPU SRAM via the bus. The mechanism is similar to access enable protection (see the "Bus MPU" section in the User Manual)
• CPU MPU
  • CPU MPU gives the option to filter address ranges. Here, the ranges can be set like memory windows and offer filtering within the complete address range. Only outgoing accesses from the CPU are filtered (see the "Memory Protection System" section in the TriCore™ TC1.6.2 core architecture manual (volume 1)).

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series