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AURIX™ MCU: How to exchange data between main CPU and SCR – KBA237957

AURIX™ MCU: How to exchange data between main CPU and SCR – KBA237957

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Community Translated: AURIX™ MCU:メインCPUとSCRの間でデータを交換する方法 – KBA237957

The AURIX™ TriCore™ CPUs and the SCR XC800 CPU (as part of PMS) belong to different SoC domains and in general run as fully separate applications; however, data must be exchanged between these cores and thus between two different domains.

There are basically two ways for data exchange between AURIX™ TriCore™ and SCR: (a) by using the SCR XRAM memory, or (b) by using the PMS registers and SCR interrupt registers interface.

Even if the XRAM is accessed by SCR for its own code execution and data handling, it is also accessible from the main domain via the Flexible Peripheral Interconnect (FPI) interface on the System Peripheral Bus (SPB). This memory area is then accessible from both domains, ensuring the exchange of data in both directions between TriCore™ CPU and SCR.

Moreover, since the XRAM is also powered by the standby supply voltage (VEVRSB), the content is retained both while the TriCore™ CPU is in standby mode and after the wake-up from standby.

For details on XRAM size and related address ranges, see the specific AURIX™ TC3xx User Manual.

Additionally, two SCR interrupt interface registers in combination with the PMS Standby and Wake-up Control Register 2 (PMSWCR2), located in the main SoC, can be used to transfer data between both domains:

  1. The SCR Interrupt Data Exchange Register (SCRINTEXCHG) allows fast data exchange from SCR to CPUs. The SCR can make a direct interrupt request to any CPU via the NMICON register and write 8-bit data to the SCRINTEXCHG SCR register, which is then transferred to the PMSWCR2.SCRINT register bit field to be read out from the CPU. This can be used to decode the reason for interrupt, although it is not limited to that. Any data, at any time, can be transferred from the SCR to the TriCore™ CPUs.

  2. The SCR TriCore Interrupt Data Exchange Register (TCINTEXCHG) allows fast data exchange from CPUs to SCR. Any CPU can trigger a direct interrupt request to the SCR by writing to the PMSWCR2.TCINTREQ register bit and writing 8-bit data of information to the PMSWCR2.TCINT register field, which is then transferred to the TCINTEXCHG SCR register bit field to be read out from the SCR to decode the interrupt reason.
    Infineon_Team_0-1687253595709.png
    Figure 1 SCR bus configuration

Note: This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC3xx series
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