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AURIX™ MCU: How to enable GTM-MCS to directly access EVADC and EDSADC conversion results – KBA235630

AURIX™ MCU: How to enable GTM-MCS to directly access EVADC and EDSADC conversion results – KBA235630

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Community Translation: AURIX™ MCU: GTM-MCSでEVADCとEDSADC変換結果に直接アクセスする方法 – KBA235630

Version: **

Either the GxRES15 result of any Enhanced Versatile ADC (EVADC) group or the result of any Enhanced Delta-Sigma ADC (EDSADC) channel is also available for other modules through the hardware data interface (HDI).

In TC3xx devices, the Generic Timer Module (GTM) offers up to 30 dedicated Multi Channel Sequencer (MCS) internal registers [ADC_CHx_DATA (with x = 0..29)] which are updated using the information delivered by the HDI. Such registers can be accessed only by GTM-MCS tasks.

Every time a new conversion is available, the corresponding ADC_CHx_DATA registers are updated with the new conversion result and the status of the ACK and VALID signals. These two signals can be used to validate the conversion result and determine the ADC status, as shown in the following table:

ACK

VALID

Description

0

1

Try to access an ADC line that is not connected (GTM offers more input lines than are used)

1

1

New conversion available. Any MCS task can read the data.

1

0

Conversion data available but at least one MCS task have read the data already.

0

0

First conversion is in progress or the ADC not enabled.

 

  • The ADC_CHx_DATA [29:0] bits contain the conversion result and other ADC information: EVADC channel number, EDSADC input multiplexer.
  • The ADC_CHx_DATA [30:30] bit reflects the status of the internal GTM VALID signal which is set every time a new conversion result is received through the HDI.  An MCS read access to the ADC_CHx_DATA register resets the VALID signal. It is also set if the ADC input line is not physically connected to any ADC converter group.

Note:    VALID signal is not related to the GxRES15.VF bitfield, but it is locally generated by GTM.

  • The ADC_CHx_DATA [ 31:31] bit reflects the status of the internal GTM ACK signal which is set as soon as the first conversion is received. It can be cleared only with a GTM module reset.

ADC_CHx_DATA[31:0] registers connected to EVADC converters have the following structure:

BinduPriya_G_2-1655716634560.png


ADC_CHx_DATA[31:0] registers connected to EVADC converters have the following structure

BinduPriya_G_1-1655716591334.png


To get the desired EVADC/EDSADC conversion, each MCS task should use the BRD (Bus Read) instruction to access the desired ADC_CHx_DATA register. For example:

  • BRD Ry ADC_CHx_DATA

 This operation returns the higher 8 bits of ADC_CHx_DATA [31:24] to the MHB (Memory High Byte) register and the remaining bits (ADC_CHx_DATA [23:0]) to the Ry (general purpose) register.

Note:

This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC3xx series
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