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AURIX™ MCU: Generating traps on divide-by-zero exception in the FPU - KBA234715

AURIX™ MCU: Generating traps on divide-by-zero exception in the FPU - KBA234715

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AURIX™ MCU: Generating traps on divide-by-zero exception in the FPU - KBA234715

Community Translation: AURIX™ MCU: FPUにゼロ除算例外のトラップを生成 – KBA234715
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Context: By default, trap generation is disabled in the Trap Control Register (FPU_TRAP_CON). This register determines whether traps are generated when corresponding operations occur in the floating-point unit (FPU). To generate a trap when a divide-by-zero exception occurs, enable the corresponding bit in this register.

Solution: The FPU implements all five IEEE-754 exceptions (invalid operation, overflow, divide by zero, underflow, and inexact). When one of these exceptions occur, the corresponding exception flag in the PSW (Program Status Word) register is asserted.

If a divide-by-zero exception occurs, the FZ will be asserted.

Note that when a divide by zero (0/0) operation occurs, an FI exception is asserted rather than an FZ.

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For more details, see the “FPU Registers” sections of the User’s manual and "Asynchronous Traps" section located in the "TriCore™ TC1.62 core architecture manual (volume 1)".

Note:  This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC2xx series
  • AURIX™ TC3xx series

 

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