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AURIX™ MCU: Generating repetitive complex PWM using GTM - KBA236050

AURIX™ MCU: Generating repetitive complex PWM using GTM - KBA236050

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Community Translation: AURIX™ MCU: GTMによる反復的で複雑なPWM生成 - KBA236050

Version: **

You can define the pulse width modulation (PWM) profile into a generic timer module (GTM)-FIFO. Advanced routing unit (ARU) will automatically transfer data (period/duty) from FIFO to ATOM, which generates the PWM signal. Setting FIFO in ring mode allows repeating periodically the PWM profile. GTM-FIFO has a direct connection with ARU; using FIFO to ARU unit (F2A), ATOM is connected to ARU, which allows the generation of complex output signals without CPU interaction.

ATOM configuration

Within the GTM_ATOMx_CHx register, enable ARU access by configuring the GTM_ATOMx_CHx.ARU_EN register and provide the ARU source address to ATOM by configuring the GTM_ATOMx_CHx_RDADDR.RDADDR0 register. For example, if you are using FIFO CH0, then set it to 0x51 in the GTM_ATOMx_CHx_RDADDR.RDADDR0 register, which is the FIFO_CHO address. As shown in Figure 1, the first 24-bits in the ARU word will be copied to SR0 (PWM period if ATOM is in SOMP mode), and the second 24-bits will be copied to SR1 (PWM duty cycle if ATOM is in SOMP mode).

BinduPriya_G_2-1661494025190.png

 


Figure 1  ATOM configuration


Writing PWM period and duty cycle values to FIFO

GTM-FIFO buffer is writable using the main CPU through AEI TO FIFO data interface (AFD). Write period and duty cycle values using the GTM_AFDx_CHx_BUF_ACC register.

First GTM_AFDx_CHx_BUF_ACC writes: Period 0

Duty cycle 0

Period 1

Duty cycle 1

Period 2

Duty cycle 2

Period 3

Last GTM_AFDx_CHx_BUF_ACC writes: Duty cycle 3

 

GTM-FIFO settings

Set the FIFO to ring buffer mode by configuring FIFO[i]_CH[z]_CTRL.RBM and the FIFO ring buffer mode will provide a continuous data stream to ATOM without CPU interaction.

FIFO to ARU unit (F2A)

BinduPriya_G_1-1661493671755.png

 

Figure 2 FIFO to F2A

ARU can access FIFO directly through F2A. Configure the GTM_F2Ax_CHx_STR_CFG.DIR, GTM_F2Ax_CHx_STR_CFG.TMODE registers and then enable the F2A stream using the GTM_F2A_ENABLE.STRx_EN register.

Output PWM

Figure 3 shows three PWM with different duty cycles and periods. This PWM duty and period are updated from GTM-FIFO without any interaction from the CPU.

BinduPriya_G_0-1661493557696.png

 

Figure 3  PWM
 
Note:   This KBA applies to the following series of AURIX™ MCUs:
  • AURIX™ TC2xx series
  • AURIX™ TC3xx series

 

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