AURIX™ MCU: Difference in variable allocation at LMU vs CPU core memory - KBA234423
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Dec 22, 2021
10:33 PM
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Dec 22, 2021
10:33 PM
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LMU has hardware interconnection with CPU core via Shared Resource Interconnection (SRI). Therefore, memory variable access at CPU core via Data Scratch-Pad RAM (DSPR) is faster compared to LMU.
See the “Local Memory Unit (LMU)” and “CPU Subsystem” sections of the user’s manual for more information on registers.
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series
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