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Community Translation: AURIX™ MCU: レーダー処理の派生物 – KBA236205
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With the AURIX™ 2G, a new subsystem, additional memory, and hardware accelerator (SPU) for radar data processing, are added. Therefore, the following derivates are supporting a range of RADAR use cases:
The SPU uses a three-stage streaming architecture to provide the data pre-processing, FFT, and data post-processing operations. The SPU uses the radar memory to store datasets and has internal buffer memories, which are used to store the data currently progressing through the processing pipline.
Figure 1 Radar processing
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC3xx series
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