AURIX™ MCU: Data Flash erase disturb limit parameter definition - KBA234714
Community Translation: AURIX™ MCU: データフラッシュ消去妨害制限パラメータ定義 - KBA234714
Question: Why is the Data Flash erase disturb limit parameter defined in the datasheet and how do we arrive at the value of 50 erases?
Answer: In memory devices, cells are not completely electrically isolated. Thus, erasing the data in one part of the memory may affect the content of neighboring cells after repeated erase operations in that area over time. Infineon has defined 50 erases in one area as the threshold after which the content in the neighboring cells must be considered as unreliable. This is defined in the “Flash Target Parameters” section of the datasheet as "Data Flash erase disturb limit".
To avoid reaching the value of 50 erases, data must be renewed regularly through the flash EEPROM emulation algorithm. Note that each application may have specific read and erase cycles; therefore, you should determine the appropriate usage and implementation of these measures by referring to the “Robust EEPROM Emulation” section of the user’s manual.
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series