Community Translation: AURIX™ MCU: Flashからの読み出しおよびFlash動作間の競合 – KBA235087
Version: **
The nature of conflicts depend on whether the MCU is accessing the same bank or not. "Read from flash" means a read access is done via the Shared Resource Interconnection (SRI) bus. A "Flash Operation" means an operation such as erasing or programming the flash bank is in a "BUSY" state with a command.
Case 1: Same bank; Master 1 and 2 access to same bank (e.g. PF0) according to the following table:
|
Master 1 / 2
|
Read from Flash
|
Flash Operation
|
|
Read from Flash
|
No Error
|
Error 1)
|
|
Flash Operation
|
Error 1)
|
Error 2)
|
Case 2: Different banks; Master 1 and 2 access different banks (e.g. PF0 and PF1) according to the following table:
|
Master 1 / 2
|
Read from Flash
|
Flash Operation
|
|
Read from Flash
|
No Error
|
No Error
|
|
Flash Operation
|
No Error
|
Error 2)
|
Error 1:
When the Flash Operation is being executed, the flash bank reports the BUSY flag in the Flash State Register (FSR). In this mode, read accesses to this flash bank are rejected and one of the following occurs:
- A bus error.
- The READY flag is suppressed until the BUSY flag is cleared.
How the error is handled can be configured (see FCON.STALL).
At the end of the flash operation, the flash bank returns to read mode and the BUSY flag is cleared.
Error 2:
A bus error occurs for the following cases:
- A write access to the DF0 address range is attempted when the normal command interpreter is busy with a command.
- A write access to DF1 address range is attempted when the hardware security module (HSM) command interpreter is busy with a command.
If Flash Operation commands conflict with the CPU and HSM, see "Time Slice Control" in the AURIX™ MCU user manual. For more details, see the "Flash Operations" section in the User’s manual.
Note: This KBA applies to the following series of AURIX MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series
