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AURIX™ MCU: Configuring an alarm reaction in the SMU – KBA236213

AURIX™ MCU: Configuring an alarm reaction in the SMU – KBA236213

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Community Translation: 表題: AURIX™ MCU: SMU でのアラームリアクションの設定 – KBA236213

version: **

The Safety Management Unit (SMU) can be used to trigger multiple reactions to an alarm. The options are:

  • Send an interrupt request to the interrupt router (IR)
  • A non-maskable interrupt (NMI) to one or multiple CPUs
  • Reset one or more CPUs
  • A system reset or an application reset
  • Activate Fault Signaling Protocol (FSP)
  • Activate Port Emergency Stop (PES)

Figure 1 shows an overview of the registers that must be configured so that these alarm reactions are executed.

Infineon_Team_0-1664775280538.png
Figure 1  SMU alarm reactions and configuration registers

Configuration of the AGxCFn[y] and AGxFSP[y] registers is the initial step in configuring an alarm reaction. Note that the indexes x and y are correlated to the alarm index ALMx[y] (refer to the red color coding in Figure 1). Configure additional registers depending on the selected alarm reaction as shown in Table 1:

Table 1  Configuation of registers

Alarm reaction

Registers (fields)

Description

Interrupt request

AGC.IGCSi[j]

Configure these register fields based on the correlation between the indexes i and j, the interrupt lines SMU_ISR_j, and the alarm reactions SMU_IGCSi (refer to the green and blue color coding in Figure 1). In addition, configure the interrupt router (IR).

NMI

TRAPDIS1

TRAPDIS2

Use these registers inside the SCU to select which CPUs receive the NMI and which do not.

CPU Reset

AGC.RCS

Use this register field to select the CPUs that must receive the reset signal.

RESET

RESTCON.SMU

Use this register field inside the SCU to choose between an application reset or a system reset.

Activation of FSP

FSP

Use this register to configure the properties of the FSP signals.

 

If one of the previously mentioned alarm reactions is executed, it is possible to additionally activate the PES (with the exception of the RESET); however, this requires executing the reactions listed earlier. The AGC.PES and FSP.PES bit fields must be used to select the alarm reactions that must activate the PES. As shown in Figure 1, each bit of these bit fields is associated with one specific alarm reaction. In addition, the Emergency Stop Register (ESR) and Input/output Control Register x (IOCRx) registers inside the PORTS must be used to configure the behavior of the PORT when PES is asserted.

Note that the alarm reactions of the safety mechanism are processed only if the SMU_core State Machine (SSM) is in the RUN state. Two exceptions to this condition are the Watchdog Timeout and Recovery Timer alarms. Therefore, the SSM must be transitioned to the RUN state after the configuration of alarm reactions and associated registers. For this purpose, use the SMU_Start(0) command of the SMU_core control interface by setting the corresponding bit fields of the Command Register (CMD) register.

Note:  This KBA applies to the following series of AURIX™ MCU:

  • AURIX™ TC3xx series
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