AURIX™ MCU: Changing the PLL clock from 200 MHZ to 300 MHZ stops the code - KBA235586
Configured Flash Wait Cycles which depend on the configured clock are one of the reasons for this issue. Configure the Flash Wait Cycles according to the calculation provided in the User’s manual.
For more details, see the “Program Memory Unit (PMU)” for AURIX™ TC2xx devices and “Non Volatile Memory (NVM) Subsystem” for AURIX™ TC3xx devices sections of the User’s manual.
Note: This KBA applies to the following series of AURIX™ MCUs:
- AURIX™ TC2xx series
- AURIX™ TC3xx series