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AURIX™ MCU: CONVCTRL module in TC3xx - KBA236208

AURIX™ MCU: CONVCTRL module in TC3xx - KBA236208

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Community Translation: AURIX™ MCU: TC3xxのCONVCTRLモジュール - KBA236208

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Converter Control Block (CONVCTRL) also called phase synchronizer. In AURIX™ TC3xx, EVADC channels could interference each other in corner cases. Such potential cross coupling can be prevented by properly configuring CONVCTRL.

CONVCTRL generates the synchronization signal that can synchronize the conversion phase or sampling phase of each EVADC group and cab align EDSADC with this synchronization signal.

EVADC is of successive approximation registers (SAR) type ADC. During conversion, there is charge redistribution and in some corner cases, the charge redistribution may disturb EVADC reference. As multiple EVADC groups share the same reference line, other EVADC groups running in parallel could be disturbed.

  • It is recommended to align both EVADC sampling phase (EVADC_GxANCFG.SSE = 1) and conversion phase (EVADC_GLOBCFG.USC = 0) with phase synchronizer to achieve optimal conversion accuracy.

As synchonization may bring in small jitter up to one phase synchronizer period (typically dozens of nanoseconds), if the application is very sensitive to sampling timing, you may check if the accuracy is sufficient with only conversion phase synchronized.

  • It is not recommended that user has both EVADC sampling and conversion phases unsynchronized. For details, see chapter “Synchronous Sampling” in the user manual.

For EDSADC, it is recommended that EDSADC is always aligned with phase synchronizer (EDSADC_GLOBCFG.USC = 0).

When CONVCTRL is enabled for synchronization, both EVADC analog clock fADCI and EDSADC modulator clock fMOD match phase synchronizer frequency. See table “Synchronized Converter Clock Scenarios” in the user manual for the allowed frequency settings.

 
Note: This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC3xx series

 

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