Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

AURIX™ MCU: CAN bit timing parameter clarification – KBA235814

AURIX™ MCU: CAN bit timing parameter clarification – KBA235814

BinduPriya_G
Community Manager
Community Manager 250 replies posted First like received 50 sign-ins
Community Manager

AURIX™ MCU: CAN bit timing parameter clarification – KBA235814

Version: **

According to the ISO 11898 standard, CAN bit time is divided into different segments as follows:

  • Tsync: Enables phase synchronization between the transmitter and receiver
  • Tprog: Used to compensate for physical delays, for example, propagation delay on the bus line, transceiver circuit, internal delay of a CAN node
  • Tb1, Tb2: Phase buffer segments are used for edge phase errors and can be lengthened or shortened by resynchronization
  • Tsjw: The maximum number of time quanta allowed for resynchronization defined by bit field SJW

Each segment consists of multiples of a time quantum (tq), which is based on the minimum time quantum (mtq) and a prescaler m (tq = m × mtq).

The CAN-IP implementation does not require separately programmable Tprop and Tb1 parts. When using the TC3xx CAN module, the user only needs to program the sum of Tprop and Tb1 (Tprop + Tb1 = Tseg1).

BinduPriya_G_0-1658125544797.png

Figure 1  CAN bit timing parameters

ISO specifies the minimum configuration range required for CAN IP of the following:

  • Classical CAN: Total number of tq must be programmable at least from 8 to 25 in the nominal bit time
  • CAN FD: Total number of tq shall be programmable at least from 8 to 80 in the nominal bit time and at least from 5 to 25 in the data bit time

In addition, the configuration of the bit time segments must meet the following restrictions:

  • In the data bit time: Tseg2 ≥ Tsjw, Tseg1 ≥ Tsjw
  • In the nominal bit time: Tseg2 ≥ Tsjw, Tseg1 ≥ Tsjw, Tseg1 ≥ Tsjw + Tprop

TC3xx CAN module uses asynchronous clock fMCAN for the baud rate generation.

The magnitude of tq is adjusted by bits fields NBTPi.NBRP (Nominal bit rate) or DBTPi.DBRP (Data bit rate), both controls the baud rate prescaler which is driven by the module asynchronous clock fMCAN.

i.e., 1 tq = (1 + BRP value) × one clock period of fMCAN

Calculation of the bit time in TC3xx for CAN FD:

  • The nominal bit rate (where NBRP, NSJW, NTSEG1, NTSEG2 are register bit field value):
  • m = (1 + NBRP)                                                     (NBRP range: 0–511)
  • Tsjw = (1 + NSJW) × tq                                       (NSJW range: 0–127)
  • Tseg1 = (1 + NTSEG1) × tq                                (NTSEG1 range: 0–255, suggested Tseg1 min. 4 tq)
  • Tseg2 = (1 + NTSEG2) × tq                                 (NTSEG2 range: 0–127, suggested Tseg2 min. 2 tq)

           Bit time = Tsync + Tseg1 + Tseg2                     (min. 8 tq)
         The sample point (SP) = (Tsync + Tseg1) /bit time

  • The data bit rate (where DBRP, DSJW, DTSEG1, DTSEG2 are register bit field value):
  • m = (1 + DBRP)                                                     (DBRP range: 0–31)
  • Tsjw = (1 + DSJW) × tq                                       (DSJW range: 0–15)
  • Tseg1 = (1 + DTSEG1) × tq                                (DTSEG1 range: 0–31, suggested Tseg1 min. 3 tq)
  • Tseg2 = (1 + DTSEG2) × tq                                (DTSEG2 range: 0–15, suggested Tseg2 min. 2 tq)

         Bit time = Tsync + Tseg1 + Tseg2                       (min. 5 tq)
        The sample point (SP) = (Tsync + Tseg1) /bit time

The choice of the sample point is also important. Choosing a later sample point results in more tolerance with respect to propagation delay and increases bus length. Conversely, choosing a sample point closer to the midpoint of the bit period increases the oscillator tolerance for each node in the system. Both conflicting goals need to be achieved by optimizing the bit timing parameters.

There are many more considerations and rules to consider for designing a reliable and robust CAN FD bus system compared to the classical CAN. CAN FD with a higher data bit rate, the bits asymmetry caused by the physical layer becomes more critical.

In general, all CAN nodes need to use the same SP and the clock frequency as 20-MHz, 40-MHz, and 80-MHz to achieve the commonly used baud rates in the nominal and the data phases. Recommended starting points are:

  • Choose 80% SP for the nominal bit rate and 70% SP for the data bit rate
  • Choose NSJW and DSJW as large as possible
  • Choose the highest available fMCAN
  • Choose NBRP and DBRP as low as possible and set NBRP = DBRP if possible

Measurement or simulation within the final target system is highly recommended. It records CAN signals at all nodes with physical layer and network topology. This needs to be considered by the user to determine the final setting. The CiA601-3 document provides the guidelines to choose the best CAN bit timing parameter and measurement techniques.

Note:  This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC3xx series
0 Likes