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AURIX™ MCU: AURIX™ STM module – KBA238106

AURIX™ MCU: AURIX™ STM module – KBA238106

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Question: What is AURIX™ STM module, and what does it do?


System Timer (STM) is designed for global system timing applications that require both high precision and long period.

STM is a 64-bit free-running upward counter, running at frequency fSTM that starts counting automatically after an Application Reset. The STM can be optionally disabled for power-saving purposes or suspended for debugging purposes.

To understand the STM’s content and purpose, you must first know the associated registers.

Registers to know:

  • Clock Control Register (CLC): Used to switch the STM ON or OFF and to control its input clock rate.
  • Timer/Capture Registers: Registers TIM0 to TIM6 provide 32-bit views at varying resolutions of the underlying STM counter.
  • Compare Registers: CMPx holds up to 32-bits, and its value is compared to the value of the STM.
  • Interrupt Control Register: The two compare match interrupts of the STM are controlled by the STM Interrupt Control Register.

General block diagram of the STM module.jpg

Figure 1 General block diagram of the STM module

Reading of STM is synchronously possible, either in different 32-bit portions of the 64-bit counter or all 64 bits. Due to the 64-bit width of the STM, It needs to be read with two load instructions. Since the timer can continue to count between the two load operations, the two values read may not be consistent (due to a possible overflow).

To enable a synchronous and consistent reading of the STM content, a capture register (CAP) is implemented. The STM can also be read in sections from seven registers, TIM0 through TIM6, which provide a view as individual 32-bit timers, each with a different resolution and timing range. In suspend mode, the STM clock stops, but all registers are still readable.

STM can be used:

  • To generate service requests and interrupt logic control (by comparing the STM content against compare registers (CMP0/1))
  • As a time base for a dedicated CPU
  • As a reset trigger (by a compare event when a compare match is triggered)

Note: This KBA applies to the following series of AURIX™ MCUs:

  • AURIX™ TC2xx series
  • AURIX™ TC3xx series