Intelligent Power Modules (IPM) Forum Discussions

BTS7010-2EPA according to the reference circuit design, the input PWM signal, the design requirements are, through the input duty cycle changes, open to adjust the output duty cycle, but the actual test situation, the input duty cycle changes, the output does not change, the output of the chip supply voltage of 12V, this is why it is, is not the chip was originally so!

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Can you tell me how to calculate the maximum current value of a load that can be driven by a multiple high-side chip such as BTS7040-2EPA? For example, is it possible to drive two 3.5A loads at the same time?

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In the IPM simulation tool, is there a recommended setting for Rth (Case to Ambient) when the heat sink is not used?

The device under consideration is IM241-S6S1J.

IPM Simulation Tools

https://plex.infineon.com/plexim/ipmmotor.html

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Dear Infineon Engineer,

I have some serious thoughts about the operation of a specific component in my project.

1. In the typical circuit schematic provided in the datasheet, The Connection for Pin 13 (ENABLE) is shown as illustrated below.

However, in some research papers, I recommend designs where Pin 14 (IN) is shorted to Pin 13 (ENABLE). In some cases, a 5K ohm resistor is also connected in series with the EN pin. Is such a schematic design proposed?

2. In the absolute maximum ratings diagram shown below, the voltage limits for the recommended pins 13 and 14 are the same and are quite high. However, the datasheet says, 'Apply Logic High Signal to Enable Device. ' What is a logic high signal? Is it based on TTL standards, CMOS standards, or is there a specific limitation?

Your guidance and insights on these matters would be helpful.

Respectfully, Doublemint

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